RACE Constraint Solver

Concept

The RACE Constraint Solver is the default constraint solver used in the VCS (Verilog Compiler Simulator) constrained-random verification flow. It operates alongside an alternative BDD-based solver and is typically characterized by lower memory consumption, while the BDD solver favors workloads where the same randomize call is invoked repeatedly and the solution space fits in memory.

First seen 6/5/2026

Last seen 6/5/2026

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RACE Constraint Solver

Overview

The RACE Constraint Solver is the default constraint solver used in the VCS constrained-random verification environment. It is invoked when SystemVerilog randomize() calls are made on classes whose constraint sets are expressed in the standard SystemVerilog constraint syntax. In a typical VCS flow, RACE is one of two selectable solver modes, the other being a BDD (Binary Decision Diagram) solver that elaborates the entire solution space of a randomize() call before selecting a solution and caches it for subsequent calls.

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VCS Constraint Profiler ← uses 88% 1e

The profiler reports performance for the RACE solver as well as the BDD solver.

hierarchical constrained-random stimulus generation ← uses 88% 1e

The hierarchical approach can also use the RACE solver for constraint solving.

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CITATIONS

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[1] RACE is the default constraint solver in the VCS constrained-random environment, and an alternative BDD solver is available that elaborates the entire solution space before selecting a solution and caches it for subsequent calls. Generating AMD microcode stimuli using VCS constraint solver

[2] The BDD solver works well when the randomize problem does not take excessive memory and the same randomize call occurs many times, as is often the case with CPU opcode generation. Generating AMD microcode stimuli using VCS constraint solver

[3] In the published multiple-class architecture comparison, the default RACE solver showed a 4x speedup and the BDD solver showed a 2x speedup, for both benchmarked opcodes. Generating AMD microcode stimuli using VCS constraint solver

[4] The memory consumed by RACE is typically smaller and not a limiting factor, so the published BDD memory comparison was reported for the BDD solver only. Generating AMD microcode stimuli using VCS constraint solver

[5] The VCS 2009.12 release provided a testcase extraction feature to extract the slowest partition from each randomize call automatically, supporting profiling of RACE/BDD solver behavior. Generating AMD microcode stimuli using VCS constraint solver

[6] Randomizing instructions by first choosing the opcode category significantly simplified the constraint problem; the new (multiple-class) implementation had 7x fewer constraints, allowing the solver to calculate solutions more efficiently and yielding improved memory and speed without sacrificing distribution or test-level control. Generating AMD microcode stimuli using VCS constraint solver

[7] The VCS Constraint Profiler reports cumulative randomize CPU runtime, individual randomize CPU runtime, individual partition CPU runtime, and memory data per randomize call — the last being particularly useful when the BDD solver is in use. Generating AMD microcode stimuli using VCS constraint solver