GenHuzz
ToolFirst seen 6/10/2026
Last seen 9/1/2026
Evidence 46 chunks
NEIGHBORHOOD
43 nodes · 87 edgesgraph · GenHuzz · depth=1
RELATIONSHIPS
50 connectionsGenHuzz is evaluated on RocketChip, identifying new bugs and vulnerabilities.
GenHuzz is evaluated on CVA6, identifying new bugs and vulnerabilities including PMP bypass.
GenHuzz is benchmarked against TheHuzz on coverage metrics.
GenHuzz implements the Hardware-Guided Reinforcement Learning framework to dynamically optimize its fuzzing policy based on hardware feedback.
GenHuzz is evaluated on Boom, identifying new bugs and vulnerabilities.
GenHuzz is benchmarked against ChatFuzz on coverage metrics.
GenHuzz uses the Golden Reference Model as ground truth for correct execution to detect bugs.
GenHuzz optimizes a fuzzing policy through HGRL to generate effective test cases.
GenHuzz uses a reward function combining validity, hardware coverage, and bonus rewards.
GenHuzz uses reinforcement learning to fine-tune its fuzzing policy based on hardware coverage feedback.
GenHuzz is benchmarked against DifuzzRTL on coverage metrics.
GenHuzz is described as a white-box hardware fuzzing framework.
GenHuzz is benchmarked against Cascade on coverage metrics across three RISC-V cores.
GenHuzz is a hardware fuzzing framework targeting RISC-V hardware cores.
GenHuzz uses a reset module to balance exploration and exploitation when the fuzzing policy converges.
GenHuzz generates RISC-V assembly instructions as test cases for hardware fuzzing.
GenHuzz is described as a coverage-based white-box fuzzing method that maximizes exploration of hardware states.
The GenHuzz paper introduces the GenHuzz tool as an efficient generative hardware fuzzer.
GenHuzz detects vulnerabilities related to Load-Reserved/Store-Conditional instructions on Boom and Rocket.
GenHuzz generates RISC-V assembly instructions as test cases using its language model-based fuzzer.
GenHuzz employs a language model-based fuzzer to generate RISC-V assembly instructions.
GenHuzz uses PPO to bridge the fuzzer-DUT interaction in the HGRL framework.
GenHuzz uses Spike as the RISC-V ISA reference model (Golden Reference Model) for differential testing.
GenHuzz uses Synopsys VCS to generate hardware simulation traces and compute hardware coverage metrics.
GenHuzz uses hardware coverage as feedback to guide test case generation.
GenHuzz interacts with the Device Under Test to obtain hardware coverage feedback.
GenHuzz comprehends instruction semantics to generate effective test cases.
GenHuzz leverages a GPT-based (Generative Pre-trained Transformer) language model as its fuzzer.
GenHuzz detected vulnerabilities in the Physical Memory Protection implementation of RISC-V cores.
GenHuzz detected vulnerabilities related to Load-Reserved/Store-Conditional instructions in Boom and Rocket cores.
GenHuzz uses test case generation to create RISC-V assembly instruction sequences for hardware fuzzing.
GenHuzz uses FSM coverage as one of the hardware coverage metrics for evaluation.
GenHuzz uses hardware coverage feedback from the DUT to refine its fuzzing policy.
GenHuzz uses differential testing to detect bugs by comparing RTL and GRM execution traces.
GenHuzz leverages a GPT-based language model as both a fuzzer and scorer.
GenHuzz understands inter-instruction semantics to strategically combine multiple instructions.
GenHuzz uses RTL simulation as part of differential testing to detect hardware bugs.
GenHuzz uses automated mismatch detection to identify discrepancies between DUT and GRM execution traces.
GenHuzz tokenizes and encodes instructions into numerical representations for model training.
GenHuzz compares execution traces from DUT and Spike to detect bugs.
GenHuzz uses Spike as the RISC-V ISA reference model for differential testing.
GenHuzz detects vulnerabilities related to Physical Memory Protection configurations.
Lyra: A Hardware-Accelerated RISC-V Verification Framework with Generative Model-Based Processor Fuzzing ← mentions 100% 1e
The paper mentions GenHuzz as a related ML-based fuzzing work.
HiFuzz is structurally compared with GenHuzz as a related generative fuzzer.
Lichao Wu is listed as an author of GenHuzz.
Mohamadreza Rostami is listed as an author of GenHuzz.
Huimin Li is listed as an author of GenHuzz.
Jeyavijayan Rajendran is listed as an author of GenHuzz.
Ahmad-Reza Sadeghi is listed as an author of GenHuzz.
GenHuzz mentions that GPT-2's Byte-Pair Encoding is unsuitable for RISC-V assembly and replaces it with word-level encoding.