Execution Trace Comparison

Concept

Execution trace comparison is a verification technique in which two RISC-V executions—such as a golden model and a processor implementation, or two independent implementations—are run on the same instruction sequence and their reported traces are compared to detect divergence.

First seen 5/27/2026

Last seen 6/2/2026

Evidence 3 chunks

Wiki v1

WIKI

Definition

Execution trace comparison is a hardware-verification technique used in RISC-V testing where generated or injected instruction sequences are executed on more than one execution target, and the resulting execution traces are compared to identify behavioral divergence. In randomized RISC-V test frameworks, generated test programs may be executed on both a golden model and a processor under development; a RISCV-DV-style framework would typically detect divergence by comparing the execution traces.^[1]

Use in TestRIG

READ FULL ARTICLE →

NEIGHBORHOOD

No graph connections found for this entity yet. It may appear in future ingestion runs.

explore full graph →

RELATIONSHIPS

4 connections

TestRIG ← uses 100% 4e

TestRIG compares execution traces to detect divergence between model and implementation.

riscv-dv ← uses 100% 3e

RISCV-DV detects divergence by comparing execution traces between a golden model and a processor under development.

QCVEngine ← uses 100% 3e

QCVEngine compares RVFI execution traces from two implementations to detect divergence.

Tandem Execution ← uses 95% 2e

Tandem execution relies on execution trace comparison to detect divergences.

LINKED ENTITIES

2 links

TestRIG USES Extracted graph relationship

riscv-dv USES Extracted graph relationship

CITATIONS

8 sources

8 citations — click to expand

[1] RISCV-DV-style divergence detection Randomized Testing of RISC-V CPUs using Direct

[2] TestRIG VEngine trace reporting Randomized Testing of RISC-V CPUs using Direct

[3] TestRIG RVFI trace comparison Randomized Testing of RISC-V CPUs using Direct

[4] QCVEngine two-socket trace assertion Randomized Testing of RISC-V CPUs using Direct

[5] DII enables QuickCheck generation comparison and shrinking Randomized Testing of RISC-V CPUs using Direct

[6] DII specifies expected output trace sequence Randomized Testing of RISC-V CPUs using Direct

[7] Recorded tests gain full trace-equivalence checking Randomized Testing of RISC-V CPUs using Direct

[8] PyH2P lacks full trace comparison Randomized Testing of RISC-V CPUs using Direct