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Tandem Execution

Technique

Tandem Execution is a verification technique in which executable RISC-V models, ISA simulators, or simulated hardware designs are driven with instruction sequences and their execution traces are compared to find behavioral divergences.

First seen 5/27/2026
Last seen 6/3/2026
Evidence 3 chunks
Wiki v1

WIKI

Overview

Tandem Execution is the execution-and-comparison pattern used during tandem verification: executable formal models, software ISA simulators, and simulated hardware designs are compared rather than testing completed fabricated chips. In the cited RISC-V setting, this requires instrumenting the CPU design with a Direct Instruction Injection interface used by the test harness during tandem verification. [tandem-scope]

Method

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NEIGHBORHOOD

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RELATIONSHIPS

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TestRIG ← uses 100% 4e
TestRIG uses tandem execution to compare execution traces between a model and an implementation.
TestRIG ← implements 100% 3e
TestRIG checks equivalence between a model and implementation by executing the same sequences on both and comparing traces.
Tandem Verification implements → 95% 2e
Tandem execution implements tandem verification by running the same sequences on model and implementation.
Execution Trace Comparison uses → 95% 2e
Tandem execution relies on execution trace comparison to detect divergences.

LINKED ENTITIES

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TestRIG IMPLEMENTS Extracted graph relationship

CITATIONS

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5 citations — click to expand
[1] tandem-scope Randomized Testing of RISC-V CPUs using Direct
[2] trace-comparison Randomized Testing of RISC-V CPUs using Direct
[3] testrig-architecture Randomized Testing of RISC-V CPUs using Direct
[4] sequence-sources Randomized Testing of RISC-V CPUs using Direct
[5] targets Randomized Testing of RISC-V CPUs using Direct