QCVEngine

Tool

QCVEngine is described in the TestRIG paper as a TestRIG engine associated with counterexample-driven development for RVFI-DII-compatible RISC-V implementations. The paper credits QCVEngine with providing a tight cycle of reduced counterexamples, and states that it greatly simplifies, but does not entirely eliminate, test-maintenance burden.

First seen 5/27/2026

Last seen 6/3/2026

Evidence 8 chunks

Wiki v2

WIKI

Overview

QCVEngine is discussed in the TestRIG paper in the context of TestRIG's modular engine architecture. The paper states that TestRIG's modular design enables a variety of engines to drive RVFI-DII-compatible RISC-V implementations, and then discusses QCVEngine as the engine whose use greatly simplifies test maintenance, although it does not eliminate that burden entirely. [QCVEngine in TestRIG engine architecture]

Role in counterexample-driven development

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NEIGHBORHOOD

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RELATIONSHIPS

35 connections

TestRIG part of → 100% 12e

QCVEngine is TestRIG's QuickCheck-based Verification Engine component.

riscv-dv compares with → 95% 7e

QCVEngine is compared against RISCV-DV for coverage and counterexample complexity.

Architectural Coverage evaluates → 100% 7e

QCVEngine is used to evaluate architectural coverage of RISC-V implementations.

QuickCheck uses → 100% 6e

QCVEngine leverages Haskell's QuickCheck library for generating, comparing, and shrinking instruction sequences.

riscv-tests ← compares with 95% 4e

QCVEngine is compared to riscv-tests in terms of coverage and counterexample complexity.

sailcov uses → 90% 4e

QCVEngine's coverage is measured using sailcov on the Sail RISC-V model.

Verification Engine implements → 100% 4e

QCVEngine is an implementation of the Verification Engine concept in the TestRIG framework.

Execution Trace Comparison uses → 100% 3e

QCVEngine compares RVFI execution traces from two implementations to detect divergence.

Non-shrinkable Sequences uses → 90% 3e

QCVEngine supports non-shrinkable sequences for initialization and state setup.

Smart Shrinking uses → 100% 2e

QCVEngine uses smart shrinking to simplify counterexamples beyond QuickCheck's built-in shrinking.

Assertion-Based Testing uses → 90% 2e

QCVEngine supports assertions in instruction sequences to test implementation-defined behavior.

Directed-Random Test Sequence Generation uses → 85% 2e

QCVEngine uses directed-random generators for instruction sequence generation.

RVFI-DII uses → 100% 2e

QCVEngine communicates with implementations via RVFI-DII sockets.

Randomized Testing of RISC-V CPUs using Direct Instruction Injection ← introduces 90% 2e

The paper presents QCVEngine as the TestRIG verification engine.

Test Case Shrinking implements → 100% 2e

QCVEngine implements test case shrinking using QuickCheck's built-in shrinking and augmented smart shrinking functions.

Directed-Random Test Sequence Generation implements → 80% 2e

QCVEngine implements directed-random test-sequence generation through its generator infrastructure.

Instruction Sequence Shrinking implements → 100% 2e

QCVEngine implements smart shrinking strategies to produce minimal counterexamples.

riscv-tests compares with → 90% 2e

QCVEngine is compared against riscv-tests for coverage and counterexample complexity.

Test Case Shrinking uses → 100% 2e

QCVEngine uses QuickCheck's built-in shrinking strategies augmented with smart shrinking.

Cache Bug Detection evaluates → 85% 2e

QCVEngine has been used to detect cache bugs in RISC-V implementations.

Randomized Testing of RISC-V CPUs using Direct Instruction Injection ← uses 100% 2e

The paper presents QCVEngine as the QuickCheck-based Verification Engine for TestRIG.

Instruction Sequence Shrinking uses → 100% 2e

QCVEngine uses QuickCheck's built-in shrinking to reduce failing instruction sequences.

Direct Instruction Injection uses → 100% 2e

QCVEngine uses Direct Instruction Injection to decouple instruction stream from control flow.

Assertions in Instruction Sequences uses → 90% 2e

QCVEngine supports assertions in instruction sequences to detect failures without divergence.

counterexample shrinking implements → 100% 2e

QCVEngine implements smart shrinking strategies to reduce counterexamples.

Randomized Testing of RISC-V CPUs using Direct Instruction Injection ← evaluates 95% 2e

The paper evaluates QCVEngine for architectural coverage and counterexample complexity.

TestRIG ← uses 100% 2e

TestRIG's primary verification engine is QCVEngine.

Test Case Shrinking uses → 100% 2e

QCVEngine uses QuickCheck's builtin shrinking and smart shrinking functions to reduce failing test sequences.

Randomized Instruction Generation uses → 95% 1e

QCVEngine uses generators to produce arbitrary instruction sequences for testing.

Sequence Import/Export implements → 90% 1e

QCVEngine supports sequence import/export for regression testing and human-readable reporting.

Counterexample-Driven Development implements → 90% 1e

QCVEngine supports counterexample-driven development by continuously providing reduced counterexamples during development.

Direct Instruction Injection uses → 100% 1e

QCVEngine uses Direct Instruction Injection to decouple instruction stream from control flow.

Smart Shrinking uses → 95% 1e

QCVEngine uses smart shrinking augmentations beyond QuickCheck's built-in strategies.

CHERI evaluates → 95% 1e

QCVEngine was used to test CHERI processor extensions and build an archive of counterexamples.

QCVEngine provides tailored generators that promote register reuse in instruction sequences.

LINKED ENTITIES

12 links

TestRIG USES Extracted graph relationship

QuickCheck USES Extracted graph relationship

Verification Engine IMPLEMENTS Extracted graph relationship

Test Case Shrinking USES Extracted graph relationship

Smart Shrinking USES Extracted graph relationship

Non-shrinkable Sequences USES Extracted graph relationship

Assertion-Based Testing USES Extracted graph relationship

Execution Trace Comparison USES Extracted graph relationship

Directed-Random Test Sequence Generation USES Extracted graph relationship

Architectural Coverage EVALUATES Extracted graph relationship

Cache Bug Detection EVALUATES Extracted graph relationship

Randomized Testing of RISC-V CPUs using Direct Instruction Injection INTRODUCES Extracted graph relationship

CITATIONS

7 sources

7 citations — click to expand

[1] QCVEngine in TestRIG engine architecture Randomized Testing of RISC-V CPUs using Direct

[2] Reduced counterexamples provided by QCVEngine Randomized Testing of RISC-V CPUs using Direct

[3] Counterexample-driven development context Randomized Testing of RISC-V CPUs using Direct

[4] TestRIG shrinking example Randomized Testing of RISC-V CPUs using Direct

[5] Reduced counterexample workflow Randomized Testing of RISC-V CPUs using Direct

[6] Noshrink and assert directives Randomized Testing of RISC-V CPUs using Direct

[7] QCVEngine maintenance burden and model-derived engines Randomized Testing of RISC-V CPUs using Direct