Directed-Random Test Sequence Generation

Concept

Directed-random test sequence generation is a processor-verification approach that combines randomized instruction sequences with directed mechanisms such as templates, constraints, assertions, and shrinking to reach architecturally interesting states and reduce failing cases.

First seen 5/27/2026

Last seen 6/3/2026

Evidence 4 chunks

Wiki v1

WIKI

Overview

Directed-random test sequence generation combines random stimulus with mechanisms that steer generated instruction sequences toward useful architectural states. In the RISC-V CPU testing context described by TestRIG, generators can construct addresses within a defined memory range and emit random loads and stores; a shortened counterexample for a processor bug was reduced to three overlapping memory operations: two loads with a store between them. [Directed-random memory stimulus]

The approach can also be template- or model-directed. IBM's Genesys-Pro is described as being built on templates that intelligently solve for desired deep states. Related CHERI work generated tests from a formal CHERI-MIPS ISA model, compiled from L3 to HOL4, and used constraint solving to automatically generate instruction sequences that reach a desired state without triggering undefined behavior. The same general approach was also applied to the CHERI ARM Morello instruction set starting from a Sail model. [Template and constraint-directed generation]

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RELATIONSHIPS

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Genesys-Pro ← implements 90% 4e

Genesys-Pro uses templates to solve for desired deep states in directed-random test generation.

riscv-dv ← implements 95% 3e

RISCV-DV is a directed-random test sequence generator for RISC-V.

QCVEngine ← implements 80% 2e

QCVEngine implements directed-random test-sequence generation through its generator infrastructure.

PyH2P ← uses 90% 1e

PyH2P applies automated test case reduction to randomly generated RISC-V instruction sequences.

riscv-dv ← uses 95% 1e

RISCV-DV is a directed-random test sequence generator for RISC-V.

Genesys-Pro ← uses 90% 1e

Genesys-Pro uses templates to intelligently solve for desired deep states in directed-random test generation.

LINKED ENTITIES

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riscv-dv IMPLEMENTS Extracted graph relationship

Genesys-Pro IMPLEMENTS Extracted graph relationship

CITATIONS

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7 citations — click to expand

[1] Directed-random memory stimulus Randomized Testing of RISC-V CPUs using Direct

[2] Template and constraint-directed generation Randomized Testing of RISC-V CPUs using Direct

[3] Smart shrinking Randomized Testing of RISC-V CPUs using Direct

[4] Non-shrinkable setup Randomized Testing of RISC-V CPUs using Direct

[5] Assertion-based failures Randomized Testing of RISC-V CPUs using Direct

[6] Counterexample-driven development Randomized Testing of RISC-V CPUs using Direct

[7] Coverage comparison Randomized Testing of RISC-V CPUs using Direct