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PyH2P

Tool

PyH2P is discussed in the TestRIG paper as an earlier, encouraging approach to CPU verification. The cited limitations are that it does not use community-standard interfaces proven across multiple implementations, and that its divergence detection relies only on final register and memory state rather than all RVFI-exposed architectural updates.

First seen 5/27/2026
Last seen 6/3/2026
Evidence 3 chunks
Wiki v1

WIKI

Overview

PyH2P is described in the TestRIG paper as pointing "in an encouraging direction" for processor verification, while TestRIG is presented as a maturation of that approach through a standardized communication interface for interchangeable verification engines, models, and implementations.[1]

Verification model

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NEIGHBORHOOD

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RELATIONSHIPS

12 connections
TestRIG compares with → 100% 12e
TestRIG matures the approach of PyH2P, addressing its shortcomings.
Randomized Testing of RISC-V CPUs using Direct Instruction Injection ← mentions 95% 2e
The paper discusses PyH2P as a precursor to TestRIG's approach.
Randomized Instruction Generation uses → 100% 2e
PyH2P applies automated test case reduction to randomly generated RISC-V instruction sequences.
Test Case Shrinking uses → 95% 1e
PyH2P applies automated test case reduction to randomly generated RISC-V instruction sequences.
Random Instruction Generation implements → 90% 1e
PyH2P generates random RISC-V instruction sequences for testing.
Automated Test Case Reduction implements → 95% 1e
PyH2P applies automated test case reduction to randomly generated RISC-V instruction sequences.
Model-Based Random Testing implements → 85% 1e
PyH2P randomly generates RISC-V instruction sequences for testing.
Directed-Random Test Sequence Generation uses → 90% 1e
PyH2P applies automated test case reduction to randomly generated RISC-V instruction sequences.
Test Case Shrinking implements → 90% 1e
PyH2P applies automated test case reduction to randomly generated RISC-V instruction sequences.
Instruction Sequence Shrinking uses → 95% 1e
PyH2P applies automated test case reduction to produce minimal instruction sequences.
Randomized Instruction Generation implements → 90% 1e
PyH2P generates randomly generated RISC-V instruction sequences.
counterexample shrinking implements → 90% 1e
PyH2P applies automated test case reduction to randomly generated RISC-V instruction sequences.

LINKED ENTITIES

3 links
Test Case Shrinking IMPLEMENTS Extracted graph relationship
Randomized Instruction Generation IMPLEMENTS Extracted graph relationship
TestRIG COMPARES_WITH Extracted graph relationship

CITATIONS

6 sources
6 citations — click to expand
[1] PyH2P direction and TestRIG maturation Randomized Testing of RISC-V CPUs using Direct
[2] PyH2P final-state divergence detection Randomized Testing of RISC-V CPUs using Direct
[3] Succinct counterexamples from RVFI-visible state Randomized Testing of RISC-V CPUs using Direct
[4] PyH2P interface limitation Randomized Testing of RISC-V CPUs using Direct
[5] RVFI-DII interactive verification enables shrinking Randomized Testing of RISC-V CPUs using Direct
[6] Instruction injection and shrinking with branches Randomized Testing of RISC-V CPUs using Direct