Random Instruction Generation
ConceptRandom instruction generation is a hardware verification approach in which instruction sequences or test programs are generated randomly (typically under scenario constraints) to stimulate processor designs and find functional bugs. It is widely used in RISC-V CPU verification because it requires limited human expertise and scales to large RTL designs, but it is known to generate repetitive inputs that test the same processor functionalities and produce long, convoluted counterexamples.
First seen 5/24/2026
Last seen 6/8/2026
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Random Instruction Generation
Random instruction generation is a hardware verification technique in which an instruction set generator (ISG) produces assembly programs whose instructions are chosen randomly, typically under scenario-defined constraints (e.g., instruction mix, frequencies, boot and memory-map parameters), in order to exercise a processor design under test (DUT) and uncover functional bugs.
Role in design verification
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10 connectionsriscv-dv is a random instruction generator implementing random instruction generation for RISC-V verification.
TestRIG implements random instruction generation to produce test sequences.
The RISCV Random Instruction Generator implements random instruction generation for RISC-V designs.
TestRIG generates random instruction sequences to test RISC-V implementations.
Random instruction generators are commonly used in processor verification
eavs-dv uses random instruction generation to produce test programs.
The Random Instruction Generator produces randomized instruction streams for verification.
The Instruction Set Generator uses random instruction generation to produce test programs.
ProcessorFuzz paper mentions random instruction generation as a traditional verification method.
PyH2P generates random RISC-V instruction sequences for testing.
CITATIONS
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[1] Random instruction generators have been commonly used in processor verification since they require limited human expertise and scale to large RTL designs, and their lack of coverage guidance leads to repetitive inputs that retest the same functionalities. Hardware Fuzzing / ProcessorFuzz thesis (Boston University)
[2] Random stimulus can in principle exercise all combinations given enough time, but a purely random approach has difficulty doing so quickly on highly complex designs, leading to constrained-random verification steered by human expertise. Optimizing Design Verification using Machine Learning: Doing better than Random
[3] Machine learning (supervised and reinforcement learning) can improve functional coverage and reach complex hard-to-hit states faster than random or constrained-random baselines, demonstrated on a Cache Controller and on the RISC-V Ariane design using Google's RISC-V Random Instruction Generator. Optimizing Design Verification using Machine Learning: Doing better than Random
[4] Random test generation in RISC-V produces an assembly file via an instruction generator, which is compiled into a machine-language file and loaded into the DUT's memory; the same program is run on a golden model (e.g., Spike) and the execution traces are compared. Advanced Verification Suite for RISC-V Cores (RISC-V Summit Europe 2025)
[5] The instruction set generator (ISG) produces an assembly file containing the configured instructions for the targeted test scenarios, with instructions randomly generated in accordance with the scenario's constraints. Advanced Verification Suite for RISC-V Cores (RISC-V Summit Europe 2025)
[6] Examples of random instruction generators for RISC-V include Force-riscv (OpenHW Group, supports all RV32GC instructions) and Google riscv-dv; EAVS-DV is an enhancement of COREV-DV that parameterizes the fixed address spaces present in COREV-DV. Advanced Verification Suite for RISC-V Cores (RISC-V Summit Europe 2025)
[7] TestRIG's Verification Engine stimulates RISC-V implementations over RVFI-DII sockets, and its instruction sequences can be loaded from disk, generated randomly, or produced by interactive architecture-driven state-space exploration; it supports Spike, QEMU, the Sail model, and hardware cores such as RVBS, Ibex, Piccolo, Flute, and Toooba. Randomized Testing of RISC-V CPUs using Direct ... (TestRIG)
[8] Drawbacks of random test generation include long and convoluted automatically generated counterexamples, and the need for the generator to ensure useful instructions exist at the targets of randomly generated branches; PyH2P is a tool that reduces failing randomly generated RISC-V sequences to fewer than five instructions, but does not perform full trace comparison, struggles to shrink through branches, and does not use community-standard interfaces. Randomized Testing of RISC-V CPUs using Direct ... (TestRIG)
[9] Coverage-directed test generation (CDG) automatically steers the constraints of a random test generator using coverage feedback to target uncovered RTL regions; examples include MicroGP (genetic programming), a Bayesian-network mechanism (Fine and Ziv, 2003), and a Markov-chain framework (Wagner et al., 2005). Hardware Fuzzing / ProcessorFuzz thesis (Boston University)
[10] EAVS applied a wide range of randomly generated tests to the cv32e40p core, ran the same tests on Spike, and reported that each random test from EAVS-DV successfully executed on the core; comparison relies on Spike's log showing memory contents only for loads, so EAVS compares data and addresses for loads but only addresses for stores. Advanced Verification Suite for RISC-V Cores (RISC-V Summit Europe 2025)
[11] The cv32e40p tracer has known issues that led the authors to disable it: srai is improperly decoded, compressed instructions are logged in their uncompressed binary form, lui and auipc append three zeros to the LSB of their immediate values causing operand-comparison errors, and pseudo-instructions are decoded in normal form rather than Spike's convention. Advanced Verification Suite for RISC-V Cores (RISC-V Summit Europe 2025)