Overview

Randomized Instruction Generation is a design-verification technique in which instruction sequences are generated automatically, often with random or constrained-random choices, to stimulate a processor implementation and exercise architectural behavior. In hardware design verification more broadly, constrained random stimulus is described as ubiquitous, but purely random approaches may struggle to hit all combinations in complex designs without guidance. [Constrained-random stimulus motivation]

In the RISC-V evidence, randomized instruction generation is represented by generators and verification engines that create or consume RISC-V instruction sequences and measure their effect on implementation behavior and architectural coverage. The TestRIG paper compares its QCVEngine against both the RISC-V test suite and the RISCV-DV generator using Sail-model coverage as a metric. [TestRIG coverage comparison]