Symbolic QED

Tool

Symbolic QED is a hardware verification approach that generates minimal tests, including for post-silicon verification, using a formal model of a processor pipeline. It is mentioned as a related alternative approach in the TestRIG paper on randomized RISC-V CPU testing.

First seen 5/30/2026

Last seen 6/3/2026

Evidence 1 chunks

Wiki v1

WIKI

Overview

Symbolic QED is a verification-oriented test-generation approach for processor designs. The available evidence describes it as an approach that generates minimal tests for verification, including post-silicon verification, by using a formal model of the pipeline.[1]

Role in verification

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NEIGHBORHOOD

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RELATIONSHIPS

7 connections

model-based verification implements → 90% 1e

Symbolic QED generates minimal tests for verification using a formal model of the pipeline.

formal verification implements → 85% 1e

Symbolic QED is an approach that generates minimal tests using a formal model of the pipeline.

Test Case Shrinking uses → 80% 1e

Symbolic QED generates minimal tests using formal models.

Randomized Testing of RISC-V CPUs using Direct Instruction Injection ← mentions 90% 1e

The paper mentions Symbolic QED as an alternative approach for minimal test generation.

TestRIG compares with → 75% 1e

TestRIG is mentioned alongside Symbolic QED as another approach that generates minimal tests for verification.

Model-Based Formal Verification implements → 85% 1e

Symbolic QED generates minimal tests for verification using a formal model of the pipeline.

Randomized Instruction Generation uses → 80% 1e

Symbolic QED generates minimal tests for verification using a formal model of the pipeline.

LINKED ENTITIES

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formal verification IMPLEMENTS Extracted graph relationship

Test Case Shrinking USES Extracted graph relationship

Randomized Testing of RISC-V CPUs using Direct Instruction Injection MENTIONS Extracted graph relationship

CITATIONS

2 sources

2 citations — click to collapse

[1] Symbolic QED generates minimal tests for verification, including post-silicon verification, using a formal model of the pipeline. Randomized Testing of RISC-V CPUs using Direct

[2] The TestRIG paper mentions Symbolic QED as another approach in the processor verification and test-generation space. Randomized Testing of RISC-V CPUs using Direct