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PyH2P

Tool WIKI v1 · 5/27/2026

PyH2P is discussed in the TestRIG paper as an earlier, encouraging approach to CPU verification. The cited limitations are that it does not use community-standard interfaces proven across multiple implementations, and that its divergence detection relies only on final register and memory state rather than all RVFI-exposed architectural updates.

Overview

PyH2P is described in the TestRIG paper as pointing "in an encouraging direction" for processor verification, while TestRIG is presented as a maturation of that approach through a standardized communication interface for interchangeable verification engines, models, and implementations.[1]

Verification model

The evidence states that PyH2P "relies only on final register and memory state" and can still usefully detect divergence.[2] This is discussed in the context of RVFI visibility limits: not all architectural updates are reported through the RVFI PC interface, with floating-point registers and extended CHERI capability registers given as examples of unreported state.[2]

The same passage notes that occasional instructions moving otherwise unexposed values into RVFI-visible state could produce succinct counterexamples.[3]

Limitations noted in comparison with TestRIG

The TestRIG paper explicitly lists a limitation: PyH2P "does not use community-standard interfaces that have been proven across a range of implementations."[4]

TestRIG is contrasted with PyH2P by proposing a standardized communication interface so that verification engines, models, and implementations can be interchangeable and improved independently.[1]

Relationship to shrinking and instruction injection

The TestRIG paper states that interactive verification using RVFI-DII enables automated simplification and shrinking.[5] It also states that instruction injection allows straightforward shrinking of sequences with branches.[6] These claims are presented as part of TestRIG/RVFI-DII rather than as a direct property of PyH2P in the provided evidence.

References

[1]: See citation "PyH2P direction and TestRIG maturation". [2]: See citation "PyH2P final-state divergence detection". [3]: See citation "Succinct counterexamples from RVFI-visible state". [4]: See citation "PyH2P interface limitation". [5]: See citation "RVFI-DII interactive verification enables shrinking". [6]: See citation "Instruction injection and shrinking with branches".

LINKED ENTITIES

3 links
Test Case Shrinking IMPLEMENTS
Randomized Instruction Generation IMPLEMENTS
TestRIG COMPARES_WITH

CITATIONS

6 sources
6 citations
[1] PyH2P direction and TestRIG maturation Randomized Testing of RISC-V CPUs using Direct
[2] PyH2P final-state divergence detection Randomized Testing of RISC-V CPUs using Direct
[3] Succinct counterexamples from RVFI-visible state Randomized Testing of RISC-V CPUs using Direct
[4] PyH2P interface limitation Randomized Testing of RISC-V CPUs using Direct
[5] RVFI-DII interactive verification enables shrinking Randomized Testing of RISC-V CPUs using Direct
[6] Instruction injection and shrinking with branches Randomized Testing of RISC-V CPUs using Direct