Test Case Shrinking

Concept

Test Case Shrinking is the automated simplification of failing verification inputs into smaller counterexamples. In the provided evidence, it is described in the context of TestRIG and RVFI-DII, where interactive verification and Direct Instruction Injection make shrinking possible, including for instruction sequences with branches.

First seen 5/27/2026

Last seen 5/31/2026

Evidence 6 chunks

Wiki v1

WIKI

Overview

Test Case Shrinking is the reduction or simplification of a failing test input into a smaller form that still demonstrates the same verification failure. In the TestRIG context, the evidence describes this as automated simplification and shrinking enabled by interactive verification through RVFI-DII.

Role in TestRIG

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NEIGHBORHOOD

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RELATIONSHIPS

7 connections

TestRIG ← implements 100% 2e

TestRIG implements test case shrinking to reduce failing counterexamples to minimal sequences.

QCVEngine ← implements 100% 2e

QCVEngine implements test case shrinking using QuickCheck's built-in shrinking and augmented smart shrinking functions.

Direct Instruction Injection ← implements 90% 2e

Direct Instruction Injection enables simplified shrinking of test sequences because it decouples instructions from memory addresses.

TestRIG ← uses 100% 2e

TestRIG uses test case shrinking to reduce counterexamples to minimal failing cases.

QCVEngine ← uses 100% 2e

QCVEngine uses QuickCheck's built-in shrinking strategies augmented with smart shrinking.

C-Reduce ← implements 90% 1e

C-Reduce implements test case reduction for C compiler bugs.

PyH2P ← implements 90% 1e

PyH2P applies automated test case reduction to randomly generated RISC-V instruction sequences.

LINKED ENTITIES

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TestRIG USES Extracted graph relationship

QCVEngine USES Extracted graph relationship

Direct Instruction Injection IMPLEMENTS Extracted graph relationship

C-Reduce IMPLEMENTS Extracted graph relationship

PyH2P IMPLEMENTS Extracted graph relationship

CITATIONS

7 sources

7 citations — click to expand

[1] RVFI-DII supports full interactive verification, and interactive verification enables automated simplification and shrinking. Randomized Testing of RISC-V CPUs using Direct

[2] Direct Instruction Injection is for instruction input, while RVFI is for trace output. Randomized Testing of RISC-V CPUs using Direct

[3] Instruction injection allows straightforward shrinking of instruction sequences with branches. Randomized Testing of RISC-V CPUs using Direct

[4] Symbolic QED is described as another approach that generates minimal tests for verification, including post-silicon verification, using a formal model of the pipeline. Randomized Testing of RISC-V CPUs using Direct

[5] Canceled instructions are a challenge for DII because RVFI-DII requires one RVFI trace entry for each injected DII instruction. Randomized Testing of RISC-V CPUs using Direct

[6] A described RVFI-DII design attaches a sequence ID to each RVFI instruction and carries it through the pipeline so redirects can work naturally. Randomized Testing of RISC-V CPUs using Direct

[7] Instruction injection and related shrinking support helped replace instruction-level unit tests for the CHERI extension, improving productivity and assurance and enabling more efficient extension of simulators and processors. Randomized Testing of RISC-V CPUs using Direct