Direct Instruction Injection

Technique

Direct Instruction Injection (DII) is the instruction-injection technique used in the TestRIG randomized RISC-V CPU testing ecosystem. It works in combination with the RISC-V Formal Interface (RVFI-DII) to drive random instruction streams against both reference models and implementations under test, comparing execution traces to detect divergences. The technique was introduced in the paper "Randomized Testing of RISC-V CPUs Using Direct Instruction Injection" (Joannou et al., IEEE Design & Test, 41(1):40-49, February 2024) and is reported to enable straightforward shrinking of failing instruction sequences, including those containing branches.

First seen 5/27/2026

Last seen 7/4/2026

Evidence 17 chunks

Wiki v4

WIKI

Overview

Direct Instruction Injection (DII) is the instruction-injection technique used in the TestRIG randomized testing ecosystem for RISC-V CPUs. It is presented in the paper "Randomized Testing of RISC-V CPUs Using Direct Instruction Injection" by Alexandre Joannou, Peter Rugg, Jonathan Woodruff, Franz A. Fuchs, Marno van der Maas, Matthew Naylor, Michael Roe, Robert N. M. Watson, Peter G. Neumann, and Simon W. Moore, published in IEEE Design & Test of Computers, 41(1):40-49, February 2024 (DOI 10.1109/MDAT.2023.3262741). [C1, C6]

The paper presents DII as a test-injection technique at the heart of a randomized testing framework for RISC-V implementations: DII is what allows the framework to inject chosen instructions directly into a device under test, rather than constructing stimulus as conventional software programs. [C1, C2]

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RELATIONSHIPS

10 connections

TestRIG ← uses 100% 7e

TestRIG uses Direct Instruction Injection, bypassing the PC fetch mechanism.

TestRIG ← implements 100% 4e

TestRIG uses RVFI-DII interfaces for direct instruction injection testing.

Randomized Testing of RISC-V CPUs using Direct Instruction Injection ← introduces 100% 4e

The paper introduces Direct Instruction Injection as a core technique for RISC-V CPU testing.

Instruction Sequence Generation implements → 90% 3e

Direct Instruction Injection enables simplified instruction sequence generation by decoupling the instruction stream from control flow.

Randomized Testing of RISC-V CPUs using Direct Instruction Injection ← uses 100% 3e

The paper proposes and uses direct instruction injection for randomized testing of RISC-V CPUs.

Tandem Verification implements → 90% 2e

Direct Instruction Injection enables tandem verification by providing interactive instruction injection to both model and implementation.

RVFI-DII implements → 100% 2e

Direct Instruction Injection is the DII component of the RVFI-DII interface.

Test Case Shrinking implements → 90% 2e

Direct Instruction Injection enables simplified shrinking of test sequences because it decouples instructions from memory addresses.

QCVEngine ← uses 100% 1e

QCVEngine uses Direct Instruction Injection to decouple instruction stream from control flow.

Randomized Testing Framework ← uses 98% 1e

The randomized testing framework employs direct instruction injection as its technique for test injection.

LINKED ENTITIES

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Randomized Testing Framework USES Extracted graph relationship

CITATIONS

2 sources

2 citations — click to collapse

[1] Direct Instruction Injection is the instruction-injection technique used in the TestRIG randomized testing ecosystem for RISC-V CPUs, presented in the paper "Randomized Testing of RISC-V CPUs Using Direct Instruction Injection" by Joannou et al. in IEEE Design & Test, 41(1):40-49, February 2024. Randomized Testing of RISC-V CPUs Using Direct Instruction Injection

[2] The paper presents a randomized testing framework for RISC-V implementations by using a technique called direct instruction injection for test injection, as described in the editor's notes by Fei Su of Intel. Randomized Testing of RISC-V CPUs Using Direct Instruction Injection