counterexample shrinking
ConceptCounterexample shrinking is the reduction of a failing test or instruction sequence to a smaller reproducer. In the provided evidence, it is discussed in the context of RISC-V CPU randomized testing: TestRIG’s direct instruction injection makes shrinking sequences with branches straightforward.
First seen 6/3/2026
Last seen 6/3/2026
Evidence 6 chunks
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WIKI
Overview
Counterexample shrinking is the practice of reducing a failing test case to a smaller reproducing case. In the available evidence, the concept appears in RISC-V CPU verification, where failing instruction sequences can be minimized after randomized testing exposes a discrepancy.
Role in RISC-V CPU testing
NEIGHBORHOOD
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4 connectionsTestRIG uses counterexample shrinking to reduce failing test sequences to minimal examples.
QCVEngine implements smart shrinking strategies to reduce counterexamples.
C-Reduce implements automated test case reduction, analogous to counterexample shrinking.
PyH2P applies automated test case reduction to randomly generated RISC-V instruction sequences.
CITATIONS
3 sources3 citations — click to collapse
[1] TestRIG’s instruction injection allows straightforward shrinking of instruction sequences with branches. Randomized Testing of RISC-V CPUs using Direct
[2] TestRIG proposes a standardized communication interface so verification engines, models, and implementations are interchangeable and can be improved independently. Randomized Testing of RISC-V CPUs using Direct
[3] Symbolic QED is described as an approach that generates minimal tests for verification, including post-silicon verification, using a formal model of the pipeline. Randomized Testing of RISC-V CPUs using Direct