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counterexample shrinking

Concept WIKI v1 · 6/3/2026

Counterexample shrinking is the reduction of a failing test or instruction sequence to a smaller reproducer. In the provided evidence, it is discussed in the context of RISC-V CPU randomized testing: TestRIG’s direct instruction injection makes shrinking sequences with branches straightforward.

Overview

Counterexample shrinking is the practice of reducing a failing test case to a smaller reproducing case. In the available evidence, the concept appears in RISC-V CPU verification, where failing instruction sequences can be minimized after randomized testing exposes a discrepancy.

Role in RISC-V CPU testing

The TestRIG paper states that instruction injection allows straightforward shrinking of sequences with branches. This matters because branch-heavy instruction streams can otherwise be difficult to reduce while preserving the behavior that exposes a bug.

TestRIG places this capability in a standardized verification ecosystem: it proposes a standardized communication interface so verification engines, models, and implementations can be interchangeable and improved independently. Within that context, shrinking helps turn generated failing sequences into smaller artifacts that are easier to debug or reuse as focused tests.

Related approaches

The same evidence mentions Symbolic QED as another approach that generates minimal tests for verification, including post-silicon verification, using a formal model of the pipeline. This is related in goal—producing small tests—but is described as a separate approach rather than as TestRIG’s instruction-injection-based shrinking mechanism.

Evidence-backed relationships

  • TestRIG uses counterexample shrinking in the sense that its instruction-injection approach enables straightforward shrinking of instruction sequences with branches.

LINKED ENTITIES

4 links
TestRIG USES
QCVEngine IMPLEMENTS
C-Reduce IMPLEMENTS
PyH2P IMPLEMENTS

CITATIONS

3 sources
3 citations
[1] TestRIG’s instruction injection allows straightforward shrinking of instruction sequences with branches. Randomized Testing of RISC-V CPUs using Direct
[2] TestRIG proposes a standardized communication interface so verification engines, models, and implementations are interchangeable and can be improved independently. Randomized Testing of RISC-V CPUs using Direct
[3] Symbolic QED is described as an approach that generates minimal tests for verification, including post-silicon verification, using a formal model of the pipeline. Randomized Testing of RISC-V CPUs using Direct