Genesys-Pro

Tool

Genesys-Pro is described by an IBM Research publication page as a test-generation tool for functional verification of IBM processors, including several complex processors. The same source says it requires significant expertise to model architectures and use test templates fully, and that its new language reduces effort for defining and maintaining implementation- and verification-plan-specific knowledge.

First seen 5/24/2026

Last seen 8/18/2026

Evidence 67 chunks

Wiki v4

WIKI

Genesys-Pro

Genesys-Pro is a test-generation tool for functional verification of IBM processors. An IBM Research publication page for “Genesys-Pro: Innovations in test program generation for functional processor verification” describes it as “currently the main test generation tool for functional verification of IBM processors,” including several complex processors. [C1]

Role in processor verification

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NEIGHBORHOOD

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RELATIONSHIPS

50 connections

test program generation implements → 100% 6e

Genesys-Pro implements multi-processor test program generation.

Genesys-Pro: Innovations in Test Program Generation for Functional Processor Verification ← introduces 100% 6e

The paper introduces the Genesys Pro tool for test program generation.

Constraint Solving for Test Generation uses → 90% 5e

Genesys-Pro uses templates that solve for desired deep states, implying constraint solving.

IBM authored by → 95% 4e

Genesys-Pro is an IBM tool for functional processor verification.

Threadmill compares with → 95% 4e

Threadmill is compared to GenesysPro as the pre-silicon counterpart tool.

Cross-level processor verification via endless randomized instruction stream generation with coverage-guided aging ← mentions 90% 4e

The paper mentions Genesys-Pro as a related test program generation tool.

Test Template uses → 100% 4e

Genesys-Pro processes test templates to generate test programs

Directed-Random Test Sequence Generation implements → 90% 4e

Genesys-Pro uses templates to solve for desired deep states in directed-random test generation.

Constraint-based Test Generation implements → 90% 3e

Genesys-Pro implements innovations in test program generation for functional processor verification.

Verification Plan uses → 90% 3e

Genesys-Pro's new language reduces effort needed to define and maintain a verification plan.

Test Template Language uses → 100% 3e

GenesysPro defines its own test-template language for specifying scenarios.

Reference Model uses → 100% 3e

GenesysPro employs a reference model during test generation.

Constraint Satisfaction Problem uses → 100% 3e

GenesysPro generates tests by random sampling of a constraint satisfaction problem.

IBM ← uses 98% 3e

Genesys-Pro is a multi-processor test generator from IBM.

Random Test Program Generation implements → 95% 2e

Genesys-Pro implements random test program generation as its core approach

MicroTESK: An ADL-Based Reconfigurable Test Program Generator for Microprocessors ← compares with 90% 2e

The MicroTESK paper compares its approach against Genesys-Pro and discusses limitations of the latter.

test templates uses → 100% 2e

Genesys-Pro uses test templates to describe verification scenarios.

Randomized Testing of RISC-V CPUs using Direct Instruction Injection ← mentions 90% 2e

The paper mentions IBM's Genesys-Pro as an example of template-based test generation.

TestRIG compares with → 75% 2e

Genesys-Pro is mentioned as a related directed-random test approach that TestRIG is compared with.

IBM POWER7 evaluates → 90% 2e

GenesysPro was used in the pre-silicon simulation verification of POWER7.

Specification-based test program generation for MIPS64 memory management units ← compares with 90% 2e

The paper compares its approach to IBM's Genesys-Pro

Directed-Random Test Sequence Generation implements → 90% 2e

Genesys-Pro uses templates to intelligently solve for desired deep states in directed-random test generation.

Directed-Random Test Sequence Generation uses → 90% 2e

IBM's Genesys-Pro uses templates to intelligently solve for desired deep states in directed-random test generation.

Multiprocessor Verification evaluates → 90% 2e

Genesys-Pro supports multiprocessor verification by generating concurrent instruction streams

Constraint Satisfaction Problem Solving uses → 100% 2e

Genesys-Pro uses constraint satisfaction problem solving for instruction generation

Constraint-Based Random Generation implements → 95% 2e

Genesys-Pro uses constraint-based random generation for test program construction.

Stream Generation ← part of 100% 2e

Stream generation is part of the Genesys-Pro generation engine

Instruction Generation ← part of 100% 2e

Instruction generation is part of the Genesys-Pro generation engine

Resource Dependency Bias uses → 100% 2e

Genesys-Pro uses resource dependency bias as a generic biasing constraint

Maintaining Arc Consistency uses → 100% 2e

Genesys-Pro uses a MAC-based algorithm as its CSP solver

Alignment Bias uses → 100% 2e

Genesys-Pro uses alignment bias as a generic biasing constraint

Cross-level processor verification via endless randomized instruction stream generation with coverage-guided aging ← compares with 80% 2e

The paper mentions Genesys-Pro as a related model-based test generator.

Constraint Solving for Instruction Generation uses → 90% 2e

Genesys-Pro uses template-based constraint solving to reach desired deep states.

Efficient Cross-Level Processor Verification using Coverage-guided Fuzzing ← compares with 70% 2e

The paper mentions Genesys-Pro as a related model-based test generator for processor verification.

Architectural Model uses → 100% 2e

Genesys-Pro relies on an architectural model that contains processor-specific information

Testing Knowledge Database uses → 100% 2e

Genesys-Pro uses a database of testing knowledge relevant to the processor

constraint solving uses → 90% 1e

Genesys-Pro formulates constraints and solves them

Genesys extends → 100% 1e

Genesys-Pro is the third-generation tool that extends and improves upon Genesys

Multiprocessor Verification uses → 88% 1e

Genesys-Pro is used in the context of multiprocessor verification.

Model-Based Test Program Generation implements → 100% 1e

Genesys-Pro implements the model-based test program generation approach

Architectural Simulator uses → 100% 1e

Genesys-Pro sends each generated instruction to an architectural simulator

Design Simulator uses → 100% 1e

The generated test program passes to a design simulation environment

Cache Bias uses → 100% 1e

Genesys-Pro uses cache bias as a generic biasing constraint

Translation Bias uses → 100% 1e

Genesys-Pro uses translation bias to trigger address translation mechanisms

Pseudorandom Biased Generation uses → 95% 1e

Genesys-Pro uses pseudorandom biased generation as its generation approach

Vera compares with → 90% 1e

Genesys-Pro is compared with Vera as commercial testing environments

VLIW Architecture uses → 90% 1e

Genesys-Pro's modeling framework is capable of modeling VLIW architectures

Address Translation Mechanism uses → 95% 1e

Genesys-Pro models complex address translation mechanisms

Self-Modifying Code mentions → 85% 1e

Genesys-Pro mentions self-modifying code as a type of reentrant instruction

Resource Reallocation uses → 85% 1e

Genesys-Pro uses resource reallocation to improve test quality

LINKED ENTITIES

5 links

Test Generation IMPLEMENTS Extracted graph relationship

Functional Verification USES Extracted graph relationship

test templates USES Extracted graph relationship

IBM USES Extracted graph relationship

Verification Plan USES Extracted graph relationship

CITATIONS

3 sources

3 citations — click to collapse

[1] Genesys-Pro is described as the main test generation tool for functional verification of IBM processors, including several complex processors. Genesys-Pro: Innovations in test program generation for functional processor verification for IEEE Design and Test of Computers - IBM Research

[2] Using Genesys-Pro fully requires expertise in architecture modeling and testing knowledge to use test templates. Genesys-Pro: Innovations in test program generation for functional processor verification for IEEE Design and Test of Computers - IBM Research

[3] Genesys-Pro's new language reduces the effort needed to define and maintain knowledge specific to an implementation and verification plan. Genesys-Pro: Innovations in test program generation for functional processor verification for IEEE Design and Test of Computers - IBM Research