Test Template

CodeArtifact

A test template is a partially specified verification scenario used in Genesys PE to generate randomized hardware-verification test programs. The template language combines transaction statements, control statements, programming constructs, and scoped bias statements, allowing compact expression of processor-verification scenarios while leaving unspecified values to be chosen randomly by the generator.

First seen 5/26/2026

Last seen 5/26/2026

Evidence 3 chunks

Wiki v1

WIKI

Test Template

In the Genesys PE hardware-verification environment, a test template is a partially specified verification scenario. For processor verification, the paper describes templates whose hardware transactions are single processor instructions. A template specifies required transactions and constraints while allowing unspecified values to be selected randomly during test generation.

Language structure

READ FULL ARTICLE →

NEIGHBORHOOD

No graph connections found for this entity yet. It may appear in future ingestion runs.

explore full graph →

RELATIONSHIPS

2 connections

Genesys PE ← uses 100% 2e

Genesys PE takes test templates as input to generate tests.

Test Template Language uses → 100% 1e

Test templates are written using the test template language.

CITATIONS

8 sources

8 citations — click to expand

[1] Test templates are partially specified verification scenarios in the Genesys PE test-template language. Constraint-Based Random Stimuli Generation for Hardware Verification

[2] The test-template language includes transaction statements, control statements, programming constructs, and bias statements. Constraint-Based Random Stimuli Generation for Hardware Verification

[3] The table-walk example stores randomly selected registers into memory addresses from 0x100 to 0x200 in increments of 16. Constraint-Based Random Stimuli Generation for Hardware Verification

[4] Generated tests obey template specifications while unspecified values are chosen randomly. Constraint-Based Random Stimuli Generation for Hardware Verification

[5] A reported verification plan using about 35,000 Genesys test templates was implemented in Genesys PE with 2,000 templates at the same functional coverage. Constraint-Based Random Stimuli Generation for Hardware Verification

[6] Genesys PE improved verification quality by enabling more general scenarios, including conjunctive-constraint scenarios that were sometimes impossible in Genesys. Constraint-Based Random Stimuli Generation for Hardware Verification

[7] Genesys PE allowed design-independent verification scenarios and supported a reusable body of PowerPC architectural and micro-architectural test templates used across IBM PowerPC verification. Constraint-Based Random Stimuli Generation for Hardware Verification

[8] The knowledge base describes design, behavior, and expert knowledge, and instruction-specific testing rules can be modeled as constraints. Constraint-Based Random Stimuli Generation for Hardware Verification