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Test Template

CodeArtifact WIKI v1 · 5/26/2026

A test template is a partially specified verification scenario used in Genesys PE to generate randomized hardware-verification test programs. The template language combines transaction statements, control statements, programming constructs, and scoped bias statements, allowing compact expression of processor-verification scenarios while leaving unspecified values to be chosen randomly by the generator.

Test Template

In the Genesys PE hardware-verification environment, a test template is a partially specified verification scenario. For processor verification, the paper describes templates whose hardware transactions are single processor instructions. A template specifies required transactions and constraints while allowing unspecified values to be selected randomly during test generation.

Language structure

The Genesys PE test-template language is described as having four statement categories:

  • Transaction statements, which specify transactions to generate and properties of those transactions.
  • Control statements, which control selection or repetition of sub-statements in the generated test.
  • Programming constructs, including variables, assignments, expressions, and assertions.
  • Bias statements, which control the activation percentage of expert-knowledge rules and are scoped to the region or instruction where they apply.

The provided example is a table-walk scenario that stores contents of randomly selected registers into memory addresses from 0x100 to 0x200 in increments of 16. It uses variables, a repeat loop, a select construct, instruction statements, assignments, and scoped bias rules.

Var: addr=0x100, reg;
Bias: resource_dependency(GPR)=30, alignment(4)=50;
Instruction: load R5 <- ?; with Bias: alignment(16)=100;
Repeat(addr - 0x200) {
  Instruction: store reg -> addr;
  Select
    Instruction: Add ? <- reg, ?; with Bias SumZero;
    Instruction: Sub;
  addr = addr + 0x10;
}

Generation semantics

A generated test program obeys the specifications in the template, while values not specified in the template are selected randomly. In the described output structure, the generated test includes simulator initialization for relevant registers and memory sections, a list of instructions to execute, and expected resource results calculated by the application's reference model.

Role in verification productivity

Test templates are used to encode verification plans more compactly in Genesys PE than in the earlier Genesys system. In one reported conversion, a plan that required about 35,000 Genesys test templates—1,900 written directly and 33,000 auto-generated by enumeration scripts—was implemented in Genesys PE with 2,000 test templates while preserving the same functional coverage. The smaller suite enabled faster testing after late design changes before silicon casting.

Role in verification quality and reuse

Genesys PE's CSP-based generation and rule-definition language allowed templates to express more general and complex scenarios than Genesys. The evidence specifically notes scenarios with conjunctive constraints, such as satisfying conditions for multiple exceptions, which were sometimes impossible to generate with Genesys but often achieved full coverage with Genesys PE. Genesys PE also allowed verification scenarios to be written in a design-independent manner, contributing to a reusable body of PowerPC architectural and micro-architectural test templates used across PowerPC design verification inside IBM.

Relationship to the knowledge base

The test-template language works with a knowledge base that describes the design, behavior, and expert knowledge. For example, an instruction can be modeled by its assembly opcode and operands, and instruction-specific testing rules can be represented as constraints. Bias statements in templates control how such expert-knowledge rules are activated during generation.

CITATIONS

8 sources
8 citations
[1] Test templates are partially specified verification scenarios in the Genesys PE test-template language. Constraint-Based Random Stimuli Generation for Hardware Verification
[2] The test-template language includes transaction statements, control statements, programming constructs, and bias statements. Constraint-Based Random Stimuli Generation for Hardware Verification
[3] The table-walk example stores randomly selected registers into memory addresses from 0x100 to 0x200 in increments of 16. Constraint-Based Random Stimuli Generation for Hardware Verification
[4] Generated tests obey template specifications while unspecified values are chosen randomly. Constraint-Based Random Stimuli Generation for Hardware Verification
[5] A reported verification plan using about 35,000 Genesys test templates was implemented in Genesys PE with 2,000 templates at the same functional coverage. Constraint-Based Random Stimuli Generation for Hardware Verification
[6] Genesys PE improved verification quality by enabling more general scenarios, including conjunctive-constraint scenarios that were sometimes impossible in Genesys. Constraint-Based Random Stimuli Generation for Hardware Verification
[7] Genesys PE allowed design-independent verification scenarios and supported a reusable body of PowerPC architectural and micro-architectural test templates used across IBM PowerPC verification. Constraint-Based Random Stimuli Generation for Hardware Verification
[8] The knowledge base describes design, behavior, and expert knowledge, and instruction-specific testing rules can be modeled as constraints. Constraint-Based Random Stimuli Generation for Hardware Verification