Design Simulator
ConceptA design simulator is the execution target within a design simulation environment that runs generated verification programs and produces actual results for comparison against expected results specified by the test.
First seen 5/26/2026
Last seen 6/14/2026
Evidence 3 chunks
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Overview
In the Genesys-Pro functional-verification flow, a design simulator is the simulator that produces the actual results when a generated test program is run in a design simulation environment. The design simulation environment runs the generated program and checks for mismatches between the expected results specified in the test and the actual results produced by the design simulator. [C1]
Role in the verification flow
NEIGHBORHOOD
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1 connectionsThe generated test program passes to a design simulation environment
LINKED ENTITIES
2 linksGenesys-Pro uses_generated_tests_from Evidence states that Genesys-Pro generates test programs which are then passed to a design simulation environment.
Architectural Simulator contrasted_with Evidence distinguishes the architectural simulator used during instruction generation from the design simulator used during the design simulation run.
CITATIONS
4 sources4 citations — click to collapse
[1] The generated test program passes to a design simulation environment, which runs the program and checks for mismatches between expected test results and actual results produced by the design simulator. [PDF] Genesys-pro: innovations in test program generation for functional ...
[2] Genesys-Pro generates tests by formulating and solving a separate constraint problem for each test instruction, using constraints from architectural descriptions, testing knowledge, and test-template directives; constraints may be mandatory or nonmandatory. [PDF] Genesys-pro: innovations in test program generation for functional ...
[3] After generating each instruction, Genesys-Pro sends it to an architectural simulator so the generator can maintain an accurate view of architectural resources, resolve subsequent constraints, and produce expected results. [PDF] Genesys-pro: innovations in test program generation for functional ...
[4] The design simulation environment can use assertions and coherency monitors to detect violations, and coverage data collected during simulation helps monitor verification progress. [PDF] Genesys-pro: innovations in test program generation for functional ...