Architectural Simulator

Concept

An architectural simulator is a reference simulation model for a processor architecture that describes the behavior of any microprocessor implementation of the given architecture as specified by the architectural manual. In the cited microprocessor verification methodology, it serves as the fast, inexpensive reference machine against which RTL behavior is compared using architectural traces, and is also invoked during test generation (for example, by Genesys-Pro) to maintain an accurate view of architectural resources and to produce expected results.

First seen 5/24/2026

Last seen 6/5/2026

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Architectural Simulator

An architectural simulator is a reference simulation model for a processor architecture. In the cited functional-verification methodology, it describes the behavior of any microprocessor implementation of the given architecture as the architecture is specified in the architectural manual, and it is used as the reference machine when checking RTL behavior. [C1] It is part of a broader code-generation and analysis tool set used in simulation-based verification of high-performance microprocessors, alongside verifiers such as SBVer, BRVer, MPVer, MPAV, Theo, the Profiler, and the diagnostic database (DDB). [C7]

Role in functional verification

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RELATIONSHIPS

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Functional Verification ← uses 100% 4e

The architectural simulator serves as a reference machine in the functional verification methodology.

diagnostic program ← uses 100% 3e

Diagnostic programs are also run on the architectural simulator as a reference.

simulation-based verification ← uses 97% 2e

Simulation-based verification employs an architectural simulator as a reference machine.

Genesys-Pro ← uses 100% 1e

Genesys-Pro sends each generated instruction to an architectural simulator

LINKED ENTITIES

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Functional Verification USES Extracted graph relationship

simulation-based verification USES Extracted graph relationship

CITATIONS

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6 citations — click to expand

[1] The architectural simulator describes the behavior of any microprocessor design implementing the given architecture as the latter is specified in the architectural manual, and is used as a reference machine in the verification methodology. Code Generation and Analysis for the Functional Verification of Microprocessors

[2] The architectural simulator is fast and inexpensive, while the RTL simulator representing the particular implementation is much slower and much more expensive; functional verification aims to ensure the RTL model exhibits the same behavior as an architectural simulator would when executing the same instruction sequence. Code Generation and Analysis for the Functional Verification of Microprocessors

[3] Executing the diagnostic on both simulators produces an architectural trace and an RTL trace; because of advanced implementation features, the RTL trace is converted (streamer) into an architectural-state trace and compared with the architectural simulator's trace by the architectural comparator (refdif); a mismatch indicates a flaw in the microprocessor's implementation. Code Generation and Analysis for the Functional Verification of Microprocessors

[4] In Genesys-Pro, after generating each instruction the generator sends it to an architectural simulator for simulation so it can maintain an accurate view of architectural resources, which is essential for resolving subsequent constraints and for producing expected results; the generated test program then runs in a design simulation environment that checks the expected results against the design simulator's actual results. Genesys-Pro: innovations in test program generation for functional verification

[5] Each simulated diagnostic feeds a Profiler-based analysis that extracts cases of interest (cache hits/misses, exceptions, queue sizes) as attribute values stored in the Diagnostic Database (DDB), and the Profiler library provides a uniform object-oriented interface for stepping through trace cycles and retrieving machine-state variables across trace formats. Code Generation and Analysis for the Functional Verification of Microprocessors

[6] The architectural simulator is part of an integrated suite of code-generation and analysis tools (SBVer, BRVer, MPVer, MPAV, Theo, Profiler, DDB) used in simulation-based verification of high-performance microprocessors, where the paper's Section 8 summarizes the overall simulation-based verification approach. Code Generation and Analysis for the Functional Verification of Microprocessors