Overview

In the Genesys-Pro functional-verification flow, a design simulator is the simulator that produces the actual results when a generated test program is run in a design simulation environment. The design simulation environment runs the generated program and checks for mismatches between the expected results specified in the test and the actual results produced by the design simulator. [C1]

Role in the verification flow

Genesys-Pro generates processor verification tests from templates by formulating and solving a separate constraint problem for each test instruction. These constraints come from the architectural description, testing knowledge, and directives in the test template; constraints may be mandatory or nonmandatory. [C2]

During generation, Genesys-Pro sends each generated instruction to an architectural simulator. This lets the generator maintain an accurate view of architectural resources, resolve later constraints, and produce expected results for the resources involved in the test. [C3]

After the test program has been generated, it is passed to the design simulation environment. At this stage, the design simulator executes the generated test and produces actual results. The environment compares those actual results with the expected results embedded or specified by the generated test. [C1]

Error detection and coverage

Mismatch checking is not the only detection mechanism described for the design simulation environment. The environment can also use assertions and coherency monitors to detect violations. Coverage data collected during simulation is used to monitor verification progress. [C4]

Relationship to expected-result generation

The design simulator is used after test generation, whereas the architectural simulator is used during generation. The architectural simulator helps Genesys-Pro compute expected resource results; the design simulator then produces actual results from the design under simulation so the environment can compare expected and actual behavior. [C3] [C1]