Address Translation Mechanism

Concept

An Address Translation Mechanism is a mechanism that maps addresses from one address space to another. The term appears across heterogeneous distributed systems (translating handler code addresses across architectures in HAM), virtual memory (page-table-based translation, improved by NDPage for near-data processing), and functional processor verification (modeled and targeted by generated tests in Genesys-Pro).

First seen 5/26/2026

Last seen 6/14/2026

Evidence 7 chunks

Wiki v2

WIKI

Overview

An Address Translation Mechanism is a mechanism that maps addresses from one address space to another. In the evidence, the term is used in three distinct but related contexts: heterogeneous distributed systems (handler code addresses across architectures), processor virtual memory (page-table-based translation), and functional processor verification (modeling and exercising address translation behaviors).

In heterogeneous distributed systems

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RELATIONSHIPS

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Genesys-Pro ← uses 95% 1e

Genesys-Pro models complex address translation mechanisms

LINKED ENTITIES

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Genesys-Pro MENTIONS Extracted graph relationship

CITATIONS

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5 citations — click to expand

[1] HAM provides an efficient address translation mechanism between the individual handler code addresses of processes running different binaries on different architectures, supporting generic RPC across heterogeneous systems such as the Intel Xeon Phi x100 series and the NEC SX-Aurora TSUBASA Vector Engine. Heterogeneous Active Messages (HAM) -- Implementing Lightweight Remote Procedure Calls in C++

[2] Modern systems use a 4-level page table design to support virtual-memory address translation; NDP applications generate many translations, PTEs are accessed irregularly, and the last two levels of page tables are nearly fully occupied; NDPage's L1-bypass and flattened page table design improves performance over the state-of-the-art address translation mechanism by 14.3% (1-core), 9.8% (4-core), and 30.5% (8-core). NDPage: Efficient Address Translation for Near-Data Processing Architectures via Tailored Page Table

[3] Genesys-Pro's modeling framework provides high-level building blocks specifically suited for describing processors, offering the flexibility to model complex and procedural architectural aspects such as VLIWs and various address translation mechanisms; it separates the architecture-specific model from the generic generation engine, which is useful for modeling complex address translation mechanisms. Genesys-pro: innovations in test program generation for functional processor verification

[4] Genesys-Pro's translation bias is responsible for triggering various address translation mechanisms, with scenarios of interest including translation table events, translation path protection events, translation path reuse, and sharing. Genesys-pro: innovations in test program generation for functional processor verification

[5] The Genesys-Pro paper cites Deeptrans (A. Adir et al., 'Deeptrans — A Model-Based Approach to Functional Verification of Address Translation Mechanisms,' Proc. 4th Int'l Workshop Microprocessor Test and Verification, IEEE CS Press, 2003, pp. 3–7) as related work on functional verification of address translation mechanisms. Genesys-pro: innovations in test program generation for functional processor verification