Address Translation Mechanism Wiki

Overview

An Address Translation Mechanism is a mechanism that maps addresses from one address space to another. In the evidence, the term is used in three distinct but related contexts: heterogeneous distributed systems (handler code addresses across architectures), processor virtual memory (page-table-based translation), and functional processor verification (modeling and exercising address translation behaviors).

In heterogeneous distributed systems

In the Heterogeneous Active Messages (HAM) framework, an address translation mechanism provides an efficient mapping between the individual handler code addresses of processes running different binaries on different architectures. HAM uses this mechanism, together with a communication protocol, to support generic Remote Procedure Call (RPC) functionality across heterogeneous distributed systems, including inter- and intra-node offloading between different architectures such as the Intel Xeon Phi x100 series and the NEC SX-Aurora TSUBASA Vector Engine. [C1]

In virtual memory and near-data processing

In the NDPage paper, "address translation mechanism" refers to the virtual-memory mechanism implemented by page tables. Modern computing systems commonly use a 4-level page table design to support address translation. The paper observes that:

Memory accesses to page table entries (PTEs) are highly irregular and therefore cannot benefit from the L1 cache;
The last two levels of page tables are nearly fully occupied; and
Near-Data Processing (NDP) applications generate a large number of address translations, but the limited L1 cache in NDP systems cannot adequately cover accesses to PTEs.

NDPage proposes two key mechanisms: (1) an L1 cache bypass mechanism for PTEs that accelerates PTE memory accesses while preventing cache pollution, and (2) a flattened page table design that merges the last two levels of page tables, preserving 4 KB page flexibility while reducing the number of PTE accesses. Evaluation reports that NDPage improves end-to-end performance over the state-of-the-art address translation mechanism by 14.3% in a single-core NDP system, 9.8% in a 4-core system, and 30.5% in an 8-core system. [C2]

In functional processor verification (Genesys-Pro)

In the Genesys-Pro test-generation framework, an address translation mechanism is treated as a high-level processor-architecture mechanism that can be modeled and targeted by pseudorandom test generation. Genesys-Pro's modeling framework provides high-level building blocks specifically suited for describing processors, offering the flexibility to model complex and procedural architectural aspects such as very large instruction words (VLIWs) and various address translation mechanisms. [C3]

The model-based approach separates the architecture-specific model from the generic generation engine. The architecture-specific model principally includes a declarative description of a specific processor architecture and a database of testing knowledge relevant to that processor, which is used to create high-quality tests. This separation is identified as useful for modeling complex address translation mechanisms. [C3]

The test-generation problem is translated into a constraint satisfaction problem (CSP) solved by a generic CSP engine customized for pseudorandom test generation. Constraints can originate from the architectural description (typically mandatory) or from testing knowledge and the test template (which may be marked mandatory or nonmandatory). [C3]

Translation bias

Genesys-Pro includes a translation bias feature. Translation bias is responsible for triggering various address translation mechanisms. Translation scenarios of interest include:

translation table events;
translation path protection events;
translation path reuse; and
sharing. [C4]

This places address translation mechanisms among the architectural behaviors that can be deliberately exercised by generated tests rather than left solely to unconstrained random generation.

Related verification work

The Genesys-Pro paper cites Deeptrans — A Model-Based Approach to Functional Verification of Address Translation Mechanisms (A. Adir et al., Proc. 4th Int'l Workshop Microprocessor Test and Verification: Common Challenges and Solutions, IEEE CS Press, 2003, pp. 3–7) as related work specifically focused on functional verification of address translation mechanisms. [C5]