Directed-Random Test Sequence Generation

Technique

Directed-random test sequence generation is a model-based random testing technique used to generate instruction sequences that exercise processor implementations and compare their behavior against a model. In RISC-V verification, it is used to find counterexamples such as pipeline bugs, memory bugs, and unexpected implementation divergences, rather than to prove full equivalence.

First seen 5/30/2026

Last seen 6/3/2026

Evidence 5 chunks

Wiki v1

WIKI

Overview

Directed-random test sequence generation is a model-based random testing technique used in processor verification. Instead of formally proving equivalence between a model and an implementation, the technique generates test sequences and looks for behavioral divergence; when a mismatch is found, the test provides a counterexample to equivalence.

In the RISC-V context, directed-random test-sequence generation has been used to debug pipeline and memory bugs and to uncover unexpected divergences in implementation behavior. Generated tests are commonly run on both a golden model and a processor under development so that execution traces or other observable behavior can be compared.

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RELATIONSHIPS

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riscv-dv ← uses 100% 4e

RISCV-DV uses directed-random test-sequence generation to create RISC-V test programs.

Instruction Sequence Generation uses → 90% 2e

Directed-random test sequence generation is used to generate instruction sequences for RISC-V processor testing.

QCVEngine ← uses 85% 2e

QCVEngine uses directed-random generators for instruction sequence generation.

Genesys-Pro ← implements 90% 2e

Genesys-Pro uses templates to intelligently solve for desired deep states in directed-random test generation.

Genesys-Pro ← uses 90% 2e

IBM's Genesys-Pro uses templates to intelligently solve for desired deep states in directed-random test generation.

TestRIG compares with → 80% 1e

TestRIG is discussed in the context of directed-random test-sequence generation approaches.

riscv-dv ← implements 90% 1e

RISCV-DV is a directed-random test sequence generator for RISC-V.

LINKED ENTITIES

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QCVEngine USES Extracted graph relationship

riscv-dv USES Extracted graph relationship

Instruction Sequence Generation USES Extracted graph relationship

CITATIONS

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6 citations — click to expand

[1] Directed-random test sequence generation is used as model-based random testing to find divergences and counterexamples rather than prove equivalence. Randomized Testing of RISC-V CPUs using Direct

[2] Directed-random test-sequence generation has been used to debug pipeline and memory bugs and uncover unexpected implementation divergences. Randomized Testing of RISC-V CPUs using Direct

[3] RISCV-DV generates assembly programs for RISC-V and includes generators for RV32IMAFDC and RV64IMAFDC with support for page-table interactions, privileged CSR use, and traps or interrupts. Randomized Testing of RISC-V CPUs using Direct

[4] Direct Instruction Injection directly specifies the instruction sequence expected in the output trace and simplifies sequence generation and shrinking because the program counter does not affect the instruction stream. Randomized Testing of RISC-V CPUs using Direct

[5] QCVEngine uses Haskell QuickCheck to generate, compare, and shrink instruction sequences by sending instruction lists over DII sockets and comparing RVFI traces. Randomized Testing of RISC-V CPUs using Direct

[6] QCVEngine provides targeted generators and template-based generators for reaching deeper states such as virtual-memory mappings and cache conflicts. Randomized Testing of RISC-V CPUs using Direct