Constraint Solving for Instruction Generation

Concept

Constraint solving for instruction generation is a model-based test-generation technique used to automatically construct instruction sequences that reach desired architectural states while avoiding undefined behavior. The provided evidence describes its use in CHERI-MIPS work based on an L3 specification, its application to CHERI ARM Morello from a Sail model, and its expected role in automating templates for deep architectural states in TestRIG-related workflows.

First seen 5/27/2026

Last seen 5/27/2026

Evidence 2 chunks

Wiki v1

WIKI

Overview

Constraint solving for instruction generation is a technique for automatically producing instruction sequences from a formal architectural model. In the evidence, the technique is described as generating instruction sequences that reach a desired state while avoiding undefined behavior. This was used in prior CHERI work and is discussed as a future direction for TestRIG-style generation of templates targeting deep states in architectural models.

Use in CHERI-MIPS testing

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NEIGHBORHOOD

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RELATIONSHIPS

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Genesys-Pro ← uses 90% 2e

Genesys-Pro uses template-based constraint solving to reach desired deep states.

L3 Specification Language uses → 80% 1e

Previous CHERI work used tests generated from a formal model written in L3, compiling to HOL4 and using constraint solving to generate instruction sequences.

Sail Language uses → 80% 1e

A Sail model was used as the basis for constraint-solving-based instruction generation for CHERI ARM Morello.

LINKED ENTITIES

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Genesys-Pro USES Extracted graph relationship

L3 Specification Language USES Extracted graph relationship

Sail Language USES Extracted graph relationship

CITATIONS

6 sources

6 citations — click to expand

[1] Constraint solving was used to automatically generate instruction sequences that reach a desired state without triggering undefined behavior. Randomized Testing of RISC-V CPUs using Direct

[2] Previous CHERI work used a CHERI-MIPS ISA formal model written in the L3 specification language, compiled from L3 to HOL4, before applying constraint solving for instruction generation. Randomized Testing of RISC-V CPUs using Direct

[3] The same constraint-solving approach was applied to the CHERI ARM Morello instruction set starting from a Sail model. Randomized Testing of RISC-V CPUs using Direct

[4] A Sail-OCaml VEngine with direct access to Sail RISC-V model data structures is described as eliminating independent encodings in the VEngine and enabling future automation of templates for deep architectural states using constraint solving. Randomized Testing of RISC-V CPUs using Direct

[5] IBM’s Genesys-Pro is referenced in connection with template-based solving for desired deep states. Randomized Testing of RISC-V CPUs using Direct

[6] The surrounding TestRIG workflow includes smart shrinking, non-shrinkable sequences, and assertions. Randomized Testing of RISC-V CPUs using Direct