Sail Language

Tool

Sail is represented in the available evidence through Sail-based architectural models, including the Sail RISC-V formal model and a Sail model used for CHERI ARM Morello work. These models are used in processor testing and instruction-generation workflows, including TestRIG Direct Instruction Injection and constraint-solving-based generation.

First seen 5/27/2026

Last seen 5/30/2026

Evidence 3 chunks

Wiki v1

WIKI

Overview

The available evidence describes Sail through its use in formal architectural models. In TestRIG work on randomized testing of RISC-V CPUs, the authors report adding a Direct Instruction Injection interface to the Sail RISC-V formal model, alongside Spike and QEMU emulators, so that executable formal models, ISA simulators, and simulated hardware designs can be compared during tandem verification. [C1]

Use in RISC-V testing

READ FULL ARTICLE →

NEIGHBORHOOD

No graph connections found for this entity yet. It may appear in future ingestion runs.

explore full graph →

RELATIONSHIPS

3 connections

Sail RISC-V Model ← uses 100% 2e

The Sail RISC-V model is written in the Sail language.

Constraint Solving for Instruction Generation ← uses 80% 1e

A Sail model was used as the basis for constraint-solving-based instruction generation for CHERI ARM Morello.

Brian Campbell ← mentions 80% 1e

Brian Campbell has begun work on a Sail-OCaml VEngine with direct access to Sail RISC-V model data structures.

LINKED ENTITIES

3 links

Sail RISC-V Model USES Extracted graph relationship

Constraint Solving for Instruction Generation USES Extracted graph relationship

Brian Campbell MENTIONS Extracted graph relationship

CITATIONS

3 sources

3 citations — click to collapse

[1] Direct Instruction Injection was added to the Sail RISC-V formal model for TestRIG-style comparison of executable formal models, ISA simulators, and simulated hardware designs. Randomized Testing of RISC-V CPUs using Direct

[2] A CHERI ARM Morello instruction-generation approach was applied starting from a Sail model, following earlier CHERI work that used constraint solving to generate instruction sequences reaching desired states without undefined behavior. Randomized Testing of RISC-V CPUs using Direct

[3] Brian Campbell began work on a Sail-OCaml VEngine with direct access to Sail RISC-V model data structures, eliminating independent encodings in the VEngine and supporting future constraint-solving-based template generation. Randomized Testing of RISC-V CPUs using Direct