Brian Campbell

Person

Brian Campbell is referenced in TestRIG research as a key contributor to Sail-model-based CHERI/Morello test-generation work and as the developer of an early Sail-OCaml VEngine connected directly to the Sail RISC-V model.

First seen 5/27/2026

Last seen 6/3/2026

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Wiki v1

WIKI

Overview

Brian Campbell is mentioned in the paper Randomized Testing of RISC-V CPUs using Direct in the context of formal ISA models, constraint-solving-based test generation, and TestRIG's future development path.

Work on Sail-based verification tooling

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NEIGHBORHOOD

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RELATIONSHIPS

4 connections

Sail mentions → 90% 2e

Brian Campbell has begun work on a Sail-OCaml VEngine with direct access to Sail RISC-V model data structures.

Sail Language mentions → 80% 1e

Brian Campbell has begun work on a Sail-OCaml VEngine with direct access to Sail RISC-V model data structures.

University of Cambridge part of → 70% 1e

Brian Campbell is associated with the CHERI work at University of Cambridge.

Verification Engine (VEngine) part of → 80% 1e

Brian Campbell has begun work on a Sail-OCaml VEngine with direct access to the Sail RISC-V model data structures.

LINKED ENTITIES

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Sail Language MENTIONS Extracted graph relationship

CITATIONS

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3 citations — click to collapse

[1] Brian Campbell is identified as a key contributor to Sail-model-based CHERI ARM Morello test-generation work. Randomized Testing of RISC-V CPUs using Direct

[2] Brian Campbell had begun work on a Sail-OCaml VEngine with direct access to the data structures of the Sail RISC-V model. Randomized Testing of RISC-V CPUs using Direct

[3] The Sail-OCaml VEngine approach eliminates independent encodings in the VEngine and was expected to support automated template generation for deep architectural-model states using constraint solving. Randomized Testing of RISC-V CPUs using Direct