00

Sail

Tool ☆ WATCH ⎘ SHARE

First seen 6/2/2026

Last seen 9/5/2026

Evidence 28 chunks

01

NEIGHBORHOOD

4 nodes · 6 edges

graph · Sail · depth=1

02

RELATIONSHIPS

23 connections

TestRIG ← uses 100% 6e evidence

TestRIG uses the Sail model as its golden reference for verification.

Brian Campbell ← mentions 90% 2e evidence

Brian Campbell has begun work on a Sail-OCaml VEngine with direct access to Sail RISC-V model data structures.

RISC-V implements → 100% 2e evidence

Sail provides a golden RISC-V model used as the reference in TestRIG.

Minimally Invasive Generation of RISC-V Instruction Set Simulators from Formal ISA Models ← compares with 90% 2e evidence

The paper compares its approach with Sail as prior work

Formal ISA Model implements → 100% 2e evidence

Sail is a DSL for describing formal ISA semantics

An integrated concurrency and core-ISA architectural envelope definition, and test oracle, for IBM POWER multiprocessors ← introduces 100% 2e evidence

The paper introduces Sail as a new instruction description language.

instruction description language (IDL) implements → 100% 2e evidence

Sail implements the concept of an instruction description language.

Sail interpreter uses → 100% 2e evidence

Sail includes an interpreter defined in Lem.

Lem depends on → 100% 2e evidence

Sail is embedded in the Lem metalanguage and the Sail interpreter is written in Lem.

RVFI-DII implements → 100% 2e evidence

The Sail model implements the RVFI-DII interface.

Reference Model implements → 93% 2e evidence

Sail can serve as a reference model for architectural verification of RISC-V processors.

ISA semantics for ARMv8-a, RISC-V, and CHERI-MIPS ← uses 85% 1e evidence

The ISA semantics paper uses the SAIL language for specifying instruction set semantics.

ACT4 framework ← uses 95% 1e evidence

The ACT4 framework uses the Sail reference model to generate expected results.

TestRIG ← evaluates 1e evidence

TestRIG evaluates the Sail model as a reference implementation.

golden model implements → 1e evidence

Sail serves as the golden model for RISC-V verification in TestRIG.

CHERI evaluates → 1e evidence

Sail can be built with CHERI support for evaluation of CHERI extensions.

Mutation-Based Testing ← uses 100% 1e evidence

Mutation-based testing introduces artificial bugs into the Sail model to measure test adequacy.

CHERI implements → 90% 1e evidence

The Sail model includes a CHERI function that is tested via mutation-based testing.

executable simulator implements → 1e evidence

Sail provides a correct-by-definition executable simulator for RISC-V.

Registered Report: Generating Test Suites for GPU Instruction Sets through Mutation and Equivalence Checking ← uses 80% 1e evidence

The paper mentions that C programs can be extracted from formal semantics encoded in SAIL.

Sail JAL semantics ← part of 1e evidence

Sail JAL semantics is part of the Sail model implementation.

mutation coverage ← uses 1e evidence

Mutation coverage is implemented by modifying Sail code to simulate bugs.

Sail type system implements → 100% 1e evidence

Sail implements a type system for checking instruction descriptions.