An integrated concurrency and core-ISA architectural envelope definition, and test oracle, for IBM POWER multiprocessors
PaperFirst seen 8/11/2026
Last seen 8/11/2026
Evidence 18 chunks
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50 connectionsThe paper models the POWER ISA fixed-point non-vector user-mode instruction set.
The paper evaluates the PPOCA variant litmus test to show speculative write forwarding.
The paper introduces Sail as a new instruction description language.
The paper evaluates the MP+sync+addr-cr litmus test to demonstrate CR register granularity.
The paper handles mixed-size memory accesses in the concurrency model.
The paper models register dependencies as architecturally significant for ordering.
The paper uses Lem as the mathematical metalanguage for expressing the model.
The paper uses coherence relations in the storage subsystem model.
The paper uses register footprint analysis to calculate instruction dependencies.
The paper uses program order as a fundamental concept in the concurrency model.
The paper introduces a precise architectural envelope model integrating concurrency and ISA.
The paper uses the Sail interpreter to execute instruction descriptions.
The paper uses decode functions to map opcodes to instruction types.
The paper uses the Framemaker-sourced vendor documentation to extract the ISA specification.
The paper presents the model as an executable test oracle for hardware testing.
The paper models the condition register (CR) at a fine granularity.
The paper models the general-purpose registers (GPR) as part of the ISA.
The paper uses Lem to generate executable OCaml code from the mathematical model.
The paper integrates a concurrency model with an ISA model.
The paper integrates an ISA model for the fixed-point instruction set.
The paper introduces a web interface for interactively exploring model behaviour.
The paper targets pre-silicon testing as a use case for the test oracle.
The paper evaluates and models the behaviour of weakly consistent multiprocessors.
The paper provides tools to exhaustively compute the set of all allowed behaviours.
The paper's thread model maintains an explicit tree of in-flight instruction instances.
The paper models out-of-order execution as a key feature of weakly consistent multiprocessors.
The paper uses and extends the storage subsystem model from prior work.
The paper models speculative execution as a key feature.
The paper uses litmus tests to validate the model against hardware implementations.
The paper evaluates the MP+sync+ctrl litmus test to validate the model.
The paper uses the Sail type system to check pseudocode consistency.
Kathryn E. Gray is listed as an author of the paper.
The paper identifies POWER as a non-multicopy-atomic architecture and models this property.
Gabriel Kerneis is listed as an author of the paper.
Dominic Mulligan is listed as an author of the paper.
Christopher Pulte is listed as an author of the paper.
Susmit Sarkar is listed as an author of the paper.
Peter Sewell is listed as an author of the paper.
Most authors are affiliated with University of Cambridge.
Susmit Sarkar is affiliated with University of St Andrews.
The paper builds on the previous ppcmem tool.
The paper mentions gem5 as an existing software emulator.
The paper mentions QEMU as an existing software emulator.
The paper uses an XML extraction tool to parse vendor documentation and produce Sail definitions.
The paper uses ELF executable format as a front-end for the tool.
The paper mentions that Lem can export to Coq proof assistant definitions.
The paper mentions that Lem can export to HOL4 definitions.
The paper mentions that Lem can export to Isabelle/HOL definitions.
The paper evaluates the MP+sync+rs litmus test to show register shadow effects.
The paper evaluates the LB+datas+WW litmus test to show data-dependent write behaviour.