University of Cambridge
OrganizationIn the provided evidence, the University of Cambridge is represented through a Cambridge-hosted technical paper on TestRIG, randomized RISC-V CPU testing, CHERI/Morello-related formal architecture work, and processor-verification tooling.
First seen 5/27/2026
Last seen 6/7/2026
Evidence 5 chunks
Wiki v2
WIKI
Overview
The provided evidence for University of Cambridge centers on a technical paper hosted at cl.cam.ac.uk titled Randomized Testing of RISC-V CPUs using Direct Instruction Injection. The article connects the Cambridge-hosted research context with RISC-V CPU verification, TestRIG, QCVEngine, CHERI, Morello, Sail models, and counterexample-driven processor development.
Research themes in the evidence
NEIGHBORHOOD
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3 connectionsThe paper is associated with University of Cambridge researchers and is partially funded by DARPA.
Brian Campbell is associated with the CHERI work at University of Cambridge.
The paper is affiliated with the University of Cambridge.
CITATIONS
7 sources7 citations — click to expand
[1] The provided evidence includes a Cambridge-hosted PDF titled 'Randomized Testing of RISC-V CPUs using Direct Instruction Injection'. Randomized Testing of RISC-V CPUs using Direct
[2] The TestRIG paper discusses RVFI-DII-compatible implementations and verification engines, QCVEngine, and an open-source TestRIG repository with documentation. Randomized Testing of RISC-V CPUs using Direct
[3] The paper characterizes TestRIG as supporting counterexample-driven development and providing reduced counterexamples for processor-development debugging. Randomized Testing of RISC-V CPUs using Direct
[4] The paper reports a Flute processor bug found by a TestRIG load/store generator after 42 tests and 20 rounds of shrinking, involving overlapping memory operations, and says it was fixed within an hour. Randomized Testing of RISC-V CPUs using Direct
[5] The evidence states that previous CHERI work generated tests from a formal CHERI-MIPS ISA model written in L3, compiled to HOL4, and used constraint solving; it also says this approach was applied to the CHERI ARM Morello instruction set from a Sail model. Randomized Testing of RISC-V CPUs using Direct
[6] Brian Campbell is named as a key contributor to the CHERI/Sail-related work and as beginning work on a Sail-OCaml verification engine with direct access to Sail RISC-V model data structures. Randomized Testing of RISC-V CPUs using Direct
[7] The paper concludes that TestRIG is expected to lead toward a standardized RISC-V testing framework using instrumentation of open implementations and improving on traditional instruction-set-level unit testing. Randomized Testing of RISC-V CPUs using Direct