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University of Cambridge

Organization WIKI v2 · 5/30/2026

In the provided evidence, the University of Cambridge is represented through a Cambridge-hosted technical paper on TestRIG, randomized RISC-V CPU testing, CHERI/Morello-related formal architecture work, and processor-verification tooling.

Overview

The provided evidence for University of Cambridge centers on a technical paper hosted at cl.cam.ac.uk titled Randomized Testing of RISC-V CPUs using Direct Instruction Injection. The article connects the Cambridge-hosted research context with RISC-V CPU verification, TestRIG, QCVEngine, CHERI, Morello, Sail models, and counterexample-driven processor development.

Research themes in the evidence

The evidence describes TestRIG as a framework for testing RISC-V implementations using RVFI-DII-compatible implementations and verification engines. The paper states that TestRIG-compatible implementations and engines were collected into an open-source TestRIG repository, with documentation used and improved by new users.

The same source presents TestRIG as a development aid: it reports that TestRIG can provide reduced counterexamples, improve debugging loops for processor development, and support counterexample-driven development. In one cited example, a random load/store generator produced a short counterexample involving overlapping memory operations; the paper says this found a Flute processor bug that had escaped the RISC-V unit-test suite and was fixed within an hour.

CHERI, Morello, and formal models

The evidence also situates the TestRIG work within a broader formal-architecture and CHERI research context. It states that previous CHERI work generated tests from a formal CHERI-MIPS ISA model written in L3, compiled from L3 to HOL4, and used constraint solving to generate instruction sequences. The paper further says that the approach had been applied to the CHERI ARM Morello instruction set from a Sail model.

Brian Campbell is named in the evidence as a key contributor to this line of work and as having begun work on a Sail-OCaml verification engine with direct access to Sail RISC-V model data structures.

Related publication

The provided related-entity data links the paper Randomized Testing of RISC-V CPUs using Direct Instruction Injection to the University of Cambridge with a PUBLISHED_BY relationship. The evidence for the paper itself describes its conclusion: the authors expect TestRIG to move toward a standardized RISC-V testing framework that leverages instrumentation of open implementations and improves on traditional instruction-set-level unit testing.

LINKED ENTITIES

2 links
Randomized Testing of RISC-V CPUs using Direct Instruction Injection PUBLISHED_BY
Brian Campbell PART_OF

CITATIONS

7 sources
7 citations
[1] The provided evidence includes a Cambridge-hosted PDF titled 'Randomized Testing of RISC-V CPUs using Direct Instruction Injection'. Randomized Testing of RISC-V CPUs using Direct
[2] The TestRIG paper discusses RVFI-DII-compatible implementations and verification engines, QCVEngine, and an open-source TestRIG repository with documentation. Randomized Testing of RISC-V CPUs using Direct
[3] The paper characterizes TestRIG as supporting counterexample-driven development and providing reduced counterexamples for processor-development debugging. Randomized Testing of RISC-V CPUs using Direct
[4] The paper reports a Flute processor bug found by a TestRIG load/store generator after 42 tests and 20 rounds of shrinking, involving overlapping memory operations, and says it was fixed within an hour. Randomized Testing of RISC-V CPUs using Direct
[5] The evidence states that previous CHERI work generated tests from a formal CHERI-MIPS ISA model written in L3, compiled to HOL4, and used constraint solving; it also says this approach was applied to the CHERI ARM Morello instruction set from a Sail model. Randomized Testing of RISC-V CPUs using Direct
[6] Brian Campbell is named as a key contributor to the CHERI/Sail-related work and as beginning work on a Sail-OCaml verification engine with direct access to Sail RISC-V model data structures. Randomized Testing of RISC-V CPUs using Direct
[7] The paper concludes that TestRIG is expected to lead toward a standardized RISC-V testing framework using instrumentation of open implementations and improving on traditional instruction-set-level unit testing. Randomized Testing of RISC-V CPUs using Direct

VERSION HISTORY

v2 · 5/30/2026 · gpt-5.5 (current)
v1 · 5/27/2026 · gpt-5.5