golden model

Concept

A golden model (also called a reference model) is a high-level software model of a processor or design used as the expected-behavior baseline during verification. In co-simulation, UVM testbenches, and hardware-fuzzing flows, architectural state computed by the golden model — most commonly an ISA-level simulation result or an Instruction Set Simulator (ISS) trace log — is cross-checked against the design-under-test (DUT). Spike and Dromajo are common RISC-V instances. Golden models are widely used because randomly generated tests are not naturally self-checking, but their cost has motivated 'golden-free' verification methods in adjacent areas such as hardware-Trojan detection.

First seen 5/27/2026

Last seen 7/19/2026

Evidence 9 chunks

Wiki v5

WIKI

Definition

A golden model (also called a reference model) is a high-level software model of a processor or design used as the expected-behavior baseline during verification. It is characterized as fast and uncomplicated, omitting implementation details such as pipeline depth, buffer sizes, or branch prediction, and updating architectural state at instruction-level granularity rather than cycle-by-cycle (Kabylkas et al., MICRO-54, 2021; survey on hardware fuzzing, Boston University).

In the RTL-fuzzing literature, the golden model is explicitly described as an ISA-level simulation result used for differential comparison: "DIFUZZRTL keeps comparing an execution result of an RTL design with that of a golden model (i.e., an ISA-level simulation result), thus detecting the bugs at ISA level." (Hur et al., DIFUZZRTL)

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NEIGHBORHOOD

3 nodes · 2 edges

graph · golden model · depth=1

RELATIONSHIPS

8 connections

Dromajo ← implements 100% 4e

Dromajo acts as the golden model in the co-simulation framework.

DiFuzzRTL ← uses 100% 2e

DIFUZZRTL uses an ISA-level golden model to compare against RTL simulation results for bug detection.

Differential Fuzzing ← uses 100% 2e

Differential fuzzing uses a golden model to compare against RTL execution results.

ProcessorFuzz ← uses 90% 2e

ProcessorFuzz relies on a golden model (ISA simulator) to detect bugs via trace comparison.

Sail ← implements 1e

Sail serves as the golden model for RISC-V verification in TestRIG.

spike ← implements 1e

Spike acts as the golden model reference for verifying RISC-V core execution.

Trace Log Comparison ← uses 97% 1e

The trace log comparison checks the Ibex core simulation trace against the ISS golden model.

Co-simulation ← uses 100% 1e

Co-simulation compares the DUT against the golden model.

LINKED ENTITIES

4 links

ProcessorFuzz USES Extracted graph relationship

Trace Log Comparison REFERENCES Trace log comparison is the canonical concrete instance of golden-model-based checking, as demonstrated in the Aldec Ibex / RISCV-DV environment where the ISS trace log serves as the golden reference compared against the RTL core's trace log.

Differential Fuzzing REFERENCES Golden-model-based checking is the canonical instance of differential testing applied to hardware, where the golden model vs. RTL comparison is its RTL-verification form.

spike REFERENCES Spike is the RISC-V ISA simulator that implements the golden-model role in RISC-V verification environments such as EAVS.

CITATIONS

8 sources

8 citations — click to expand

[1] A golden model (or reference model) is a high-level software model of a processor or design used as the expected-behavior baseline during verification. UVM Simulation-based environment for Ibex RISC-V CPU core with Google RISC-V DV

[2] DIFUZZRTL keeps comparing an execution result of an RTL design with that of a golden model (i.e., an ISA-level simulation result), thus detecting the bugs at ISA level. DIFUZZRTL: Differential Fuzz Testing to Find CPU Bugs

[3] Differential testing techniques are also used for RTL verification, particularly comparing one RTL's execution results with a golden model's execution results, which inspired the design of DIFUZZRTL. DIFUZZRTL: Differential Fuzz Testing to Find CPU Bugs

[4] In the Ibex core SV/UVM testbench the Ibex core simulation trace log is compared against a golden model generated by an Instruction Set Simulator (ISS) trace log to check for correctness of execution. UVM Simulation-based environment for Ibex RISC-V CPU core with Google RISC-V DV

[5] The hardware-fuzzing flow depicts the mutation engine producing inputs whose RTL simulation trace log is compared against an ISA simulation trace log, with any mismatch flagged as a bug, and identifies 'Golden models' as one of the two main bug-detection mechanisms in hardware testing. Fuzzing for Discovering Bugs and Side Channels in Processors

[6] ProcessorFuzz is presented as part of the BU/NEHWS hardware-fuzzing flow that uses a golden model (ISA simulator) to cross-check RTL behavior on designs such as BOOM, BlackParrot, and Rocket Chip. Fuzzing for Discovering Bugs and Side Channels in Processors

[7] Many existing hardware-Trojan detection methods rely on golden models and detailed circuit specifications, often specific to certain Trojan payload types, making pre-silicon verification difficult and creating security gaps. A Golden-Free Formal Method for Trojan Detection in Non-Interfering Accelerators

[8] A run-time Trojan-detection approach using a Programmable Sensor Array (PSA) is described as golden-model free and demonstrated on an AES-128 test chip with four AES hardware Trojans. Programmable EM Sensor Array for Golden-Model Free Run-time Trojan Detection and Localization