Dromajo
ToolDromajo is the C++ `chipsalliance/dromajo` RISC-V RV64GC emulator designed for RTL co-simulation. ProcessorFuzz reported a confirmed Dromajo simulator bug involving page-table access privilege and PMP checks when no PMP entries are set.
First seen 5/27/2026
Last seen 6/8/2026
Evidence 20 chunks
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Overview
Dromajo is a RISC-V RV64GC emulator designed for RTL co-simulation. Its public repository is chipsalliance/dromajo, and the repository metadata identifies the project language as C++.
As an emulator for the RISC-V RV64GC ISA, Dromajo implements ISA simulation in a form intended to be used alongside RTL in co-simulation flows.
NEIGHBORHOOD
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26 connectionsProcessorFuzz uses Dromajo as a reference model for BlackParrot core verification.
Dromajo is designed specifically for co-simulation with RTL processors.
Dromajo acts as the golden model in the co-simulation framework.
Logic Fuzzer is embedded into the Dromajo infrastructure for operation.
Dromajo was integrated and evaluated with the BlackParrot core.
Dromajo was integrated and evaluated with the CVA6 core.
Dromajo was integrated and evaluated with the BOOM core.
Dromajo supports phase analysis concepts for checkpoint generation at simulation points.
The paper presents Dromajo as an RV64GC emulator designed for co-simulation.
Dromajo implements checkpoint generation and restoration for co-simulation.
Dromajo supports handling of asynchronous interrupts during co-simulation.
The paper uses Dromajo as the co-simulation framework for RISC-V processor verification.
Dromajo supports checkpoint generation and resumption for co-simulation.
Dromajo supports handling of asynchronous interrupts during co-simulation.
Dromajo is integrated into RTL testbenches via DPI calls.
Dromajo checkpoints include the processor architectural state including registers and CSRs.
Dromajo is an RV64GC emulator implementing the RISC-V instruction set.
Dromajo is compared to Imperas OVPsim as an alternative co-simulation solution.
Dromajo is compared to Whisper as an alternative co-simulation reference model tool.
Dromajo supports step-and-compare which improves over basic trace comparison by supporting asynchronous interrupts.
Dromajo checkpoints include CSR state and leverages RISC-V debug spec for CSR manipulation.
Dromajo avoids using Debug Transport Module by using memory and bootram checkpoints instead.
Dromajo serves as a reference ISA simulator model for BlackParrot.
Dromajo uses DPI calls for integration with RTL simulators.
Dromajo supports simulation points for capturing important program phases.
Dromajo supports Debug Transport Module but its usage is discouraged due to nondeterminism.
CITATIONS
3 sources3 citations — click to collapse
[1] Dromajo is the `chipsalliance/dromajo` RISC-V RV64GC emulator designed for RTL co-simulation, with C++ listed as the repository language. chipsalliance/dromajo
[2] ProcessorFuzz reported a confirmed Dromajo issue in which PMP checks were performed and exceptions raised even with no PMP entries set. ProcessorFuzz: Processor Fuzzing with Control and Simulator
[3] ProcessorFuzz observed that Dromajo accessed page tables at user-mode privilege level when running user-mode programs and also carried out PMP checks in user mode when no PMP entries were set. ProcessorFuzz: Processor Fuzzing with Control and Simulator