Dromajo

Tool

Dromajo is the C++ `chipsalliance/dromajo` RISC-V RV64GC emulator designed for RTL co-simulation. ProcessorFuzz reported a confirmed Dromajo simulator bug involving page-table access privilege and PMP checks when no PMP entries are set.

First seen 5/27/2026

Last seen 7/11/2026

Evidence 24 chunks

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Overview

Dromajo is a RISC-V RV64GC emulator designed for RTL co-simulation. Its public repository is chipsalliance/dromajo, and the repository metadata identifies the project language as C++.

As an emulator for the RISC-V RV64GC ISA, Dromajo implements ISA simulation in a form intended to be used alongside RTL in co-simulation flows.

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NEIGHBORHOOD

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RELATIONSHIPS

30 connections

Co-simulation implements → 100% 6e

Dromajo provides APIs for cosimulation

golden model implements → 100% 4e

Dromajo acts as the golden model in the co-simulation framework.

BlackParrot evaluates → 100% 4e

Dromajo was integrated and evaluated with the BlackParrot core.

CVA6 evaluates → 100% 4e

Dromajo was integrated and evaluated with the CVA6 core.

ProcessorFuzz ← uses 100% 4e

ProcessorFuzz uses Dromajo as a reference model for BlackParrot core verification.

Logic Fuzzer ← depends on 95% 4e

Logic Fuzzer is embedded into the Dromajo infrastructure for operation.

Effective Processor Verification with Logic Fuzzer Enhanced Co-simulation ← uses 100% 3e

Dromajo is used as the golden model in the co-simulation setup described in this paper.

ZP Cosim ← uses 99% 3e

ZP Cosim uses Dromajo as its golden reference ISA simulator for cosimulation

BOOM evaluates → 100% 3e

Dromajo was integrated and evaluated with the BOOM core.

Effective Processor Verification with Logic Fuzzer Enhanced Co-simulation ← introduces 100% 2e

The paper presents Dromajo as an RV64GC emulator designed for co-simulation.

checkpoint implements → 100% 2e

Dromajo implements checkpoint generation and restoration for co-simulation.

asynchronous interrupts uses → 95% 2e

Dromajo supports handling of asynchronous interrupts during co-simulation.

checkpoint uses → 100% 2e

Dromajo supports checkpoint generation and resumption for co-simulation.

interrupt handling uses → 100% 2e

Dromajo supports handling of asynchronous interrupts during co-simulation.

DPI calls uses → 100% 2e

Dromajo is integrated into RTL testbenches via DPI calls.

phase analysis uses → 90% 2e

Dromajo supports phase analysis concepts for checkpoint generation at simulation points.

Architectural State uses → 100% 2e

Dromajo checkpoints include the processor architectural state including registers and CSRs.

RISC-V uses → 100% 2e

Dromajo is an RV64GC emulator implementing the RISC-V instruction set.

Golden Reference Model implements → 99% 2e

Dromajo is a formally proven RISC-V functional reference model used as golden reference

CSR uses → 100% 1e

Dromajo checkpoints include CSR state and leverages RISC-V debug spec for CSR manipulation.

Debug Transport Module ← compares with 90% 1e

Dromajo avoids using Debug Transport Module by using memory and bootram checkpoints instead.

ISA-level coverage evaluates → 90% 1e

Dromajo can provide quick insights on ISA-level coverage effected by benchmarks

Imperas OVPsim compares with → 90% 1e

Dromajo is compared to Imperas OVPsim as an alternative co-simulation solution.

trace comparison uses → 80% 1e

Dromajo supports step-and-compare which improves over basic trace comparison by supporting asynchronous interrupts.

ISA simulation implements → 90% 1e

Dromajo serves as a reference ISA simulator model for BlackParrot.

whisper compares with → 90% 1e

Dromajo is compared to Whisper as an alternative co-simulation reference model tool.

Instruction Set Simulator implements → 97% 1e

Dromajo is an Instruction Set Simulator used as a golden model.

simulation points uses → 90% 1e

Dromajo supports simulation points for capturing important program phases.

Debug Transport Module uses → 80% 1e

Dromajo supports Debug Transport Module but its usage is discouraged due to nondeterminism.

DPI uses → 95% 1e

Dromajo uses DPI calls for integration with RTL simulators.

LINKED ENTITIES

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ProcessorFuzz USES Extracted graph relationship

ISA simulation IMPLEMENTS Extracted graph relationship

CITATIONS

3 sources

3 citations — click to collapse

[1] Dromajo is the `chipsalliance/dromajo` RISC-V RV64GC emulator designed for RTL co-simulation, with C++ listed as the repository language. chipsalliance/dromajo

[2] ProcessorFuzz reported a confirmed Dromajo issue in which PMP checks were performed and exceptions raised even with no PMP entries set. ProcessorFuzz: Processor Fuzzing with Control and Simulator

[3] ProcessorFuzz observed that Dromajo accessed page tables at user-mode privilege level when running user-mode programs and also carried out PMP checks in user mode when no PMP entries were set. ProcessorFuzz: Processor Fuzzing with Control and Simulator