trace comparison

Concept

Trace comparison is a reference-model checking technique for processor verification in which two models dump execution logs and those traces are compared to flag mismatches. Typical traces include program-counter flow and register or memory writebacks. The method is limited when asynchronous external stimuli, such as interrupts or debug requests, can occur independently in standalone models.

First seen 5/27/2026

Last seen 5/28/2026

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Definition

Trace comparison is a way to implement reference-model checking in processor verification. It requires both models under test to dump execution logs, then compares those traces and flags mismatches. Typical logs include program-counter flow and every register or memory writeback.

Use in verification

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Effective Processor Verification with Logic Fuzzer Enhanced Co-simulation ← uses 85% 1e

The paper discusses trace comparison as a reference model checking technique.

Dromajo ← uses 80% 1e

Dromajo supports step-and-compare which improves over basic trace comparison by supporting asynchronous interrupts.

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Effective Processor Verification with Logic Fuzzer Enhanced Co-simulation USES Extracted graph relationship

Dromajo USES Extracted graph relationship

CITATIONS

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4 citations — click to collapse

[1] Trace comparison is a reference-model checking setup that requires both models to dump execution logs, which are then compared and mismatches flagged. [PDF] Effective Processor Verification with Logic Fuzzer Enhanced Co ...

[2] Typical trace-comparison logs contain program-counter flow and every register or memory writeback. [PDF] Effective Processor Verification with Logic Fuzzer Enhanced Co ...

[3] Trace comparison can fail for asynchronous external stimuli such as interrupts and debug requests because standalone models are compared after execution and an interrupt can make the logs differ. [PDF] Effective Processor Verification with Logic Fuzzer Enhanced Co ...

[4] The cited co-simulation approach runs both models in parallel, exchanges messages at events such as instruction commit, compares states of interest, and halts on failed comparison to aid debugging near the divergence. [PDF] Effective Processor Verification with Logic Fuzzer Enhanced Co ...