Definition

Trace comparison is a way to implement reference-model checking in processor verification. It requires both models under test to dump execution logs, then compares those traces and flags mismatches. Typical logs include program-counter flow and every register or memory writeback.

Use in verification

In the verification flow described by Effective Processor Verification with Logic Fuzzer Enhanced Co-simulation, trace comparison is presented as an alternative to checking only a test's final output against a pre-calculated answer. Instead of waiting until a directed test completes and comparing the final result, trace comparison compares execution logs from the participating models.

Limitations

Trace comparison can fail when verification involves asynchronous external stimuli, such as interrupts or debug requests. Because the models run standalone and the trace comparison happens after execution, a single interrupt that fires at a different point can make the execution logs diverge even if the underlying behavior is not the intended bug being tested.

Relationship to co-simulation

The cited paper describes co-simulation as a way to address this limitation: both models run in parallel, communicate during execution, and compare states at specified events such as instruction commit. When a comparison fails, execution can halt immediately, letting an engineer begin debugging near the first divergence.