Effective Processor Verification with Logic Fuzzer Enhanced Co-simulation
Paper“Effective Processor Verification with Logic Fuzzer Enhanced Co-simulation” is a MICRO-54 paper on simulation-based RISC-V processor verification. It combines Dromajo-based reference-model co-simulation with Logic Fuzzer, an RTL-level technique for perturbing non-architectural logic so that simulations explore broader microarchitectural states.
First seen 5/27/2026
Last seen 6/8/2026
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Effective Processor Verification with Logic Fuzzer Enhanced Co-simulation presents a simulation-based verification flow for RISC-V processors. The flow combines Dromajo reference-model co-simulation with Logic Fuzzer, an RTL-level technique that inserts small pieces of logic into a design without breaking processor functionality, with the goal of reaching a broader range of microarchitectural states. [Paper venue and scope] [Logic Fuzzer definition]
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27 connectionsThe paper uses Google's riscv-dv tool to generate random tests for evaluation.
The paper evaluates Logic Fuzzer and Dromajo on the BOOM RISC-V core.
The paper introduces Logic Fuzzer as a novel tool for processor verification.
The paper uses co-simulation as a central verification technique.
The paper evaluates Logic Fuzzer and Dromajo on the CVA6 RISC-V core.
The paper evaluates Logic Fuzzer and Dromajo on the BlackParrot RISC-V core.
The paper uses RISC-V ISA tests as verification binaries.
Jose Renau is listed as an author of the paper.
The paper uses Dromajo as the co-simulation framework for RISC-V processor verification.
The paper operates on RTL designs for verification purposes.
The paper uses Dromajo checkpoints to enable efficient co-simulation of long-running programs.
The paper discusses using SPEC benchmarks with Dromajo checkpoints for verification.
Nursultan Kabylkas is listed as an author of the paper.
Tommy Thorn is listed as an author of the paper.
Shreesha Srinath is listed as an author of the paper.
Polychronis Xekalakis is listed as an author of the paper.
The paper presents Dromajo as an RV64GC emulator designed for co-simulation.
The paper uses reference model comparison as a verification technique.
The paper discusses RFUZZ as related work in input-stimuli fuzzing and distinguishes it from Logic Fuzzer.
The paper compares Dromajo with Whisper, noting Whisper's limitations in interrupt and checkpoint support.
The paper mentions Imperas Software Ltd. as a commercial alternative with similar co-simulation capabilities.
The paper focuses on simulation-based verification as the primary verification approach for complex processors.
The paper discusses trace comparison as a reference model checking technique.
The paper discusses end-of-simulation comparison as a simpler verification approach.
The paper discusses formal verification as a complementary technique with scalability limitations.
The paper discusses functional coverage as a metric used in processor verification.
The paper compares simulation-based verification with formal verification approaches.
LINKED ENTITIES
17 linksNursultan Kabylkas AUTHORED_BY Extracted graph relationship
Tommy Thorn AUTHORED_BY Extracted graph relationship
Shreesha Srinath AUTHORED_BY Extracted graph relationship
Polychronis Xekalakis AUTHORED_BY Extracted graph relationship
Jose Renau AUTHORED_BY Extracted graph relationship
Logic Fuzzer INTRODUCES Extracted graph relationship
Dromajo INTRODUCES Extracted graph relationship
CVA6 EVALUATES Extracted graph relationship
BlackParrot EVALUATES Extracted graph relationship
BOOM EVALUATES Extracted graph relationship
Co-simulation USES Extracted graph relationship
reference model comparison USES Extracted graph relationship
riscv-dv USES Extracted graph relationship
RISC-V ISA tests USES Extracted graph relationship
checkpoint USES Extracted graph relationship
SPEC benchmarks USES Extracted graph relationship
formal verification COMPARES_WITH Extracted graph relationship
CITATIONS
16 sources16 citations — click to expand
[1] Paper venue and scope [PDF] Effective Processor Verification with Logic Fuzzer Enhanced Co-simulation
[2] Random instruction generation [PDF] Effective Processor Verification with Logic Fuzzer Enhanced Co-simulation
[3] Reference model comparison [PDF] Effective Processor Verification with Logic Fuzzer Enhanced Co-simulation
[4] End-of-simulation comparison [PDF] Effective Processor Verification with Logic Fuzzer Enhanced Co-simulation
[5] Trace comparison limitation [PDF] Effective Processor Verification with Logic Fuzzer Enhanced Co-simulation
[6] Co-simulation mechanism [PDF] Effective Processor Verification with Logic Fuzzer Enhanced Co-simulation
[8] Dromajo checkpoint flow [PDF] Effective Processor Verification with Logic Fuzzer Enhanced Co-simulation
[9] Dromajo checkpoint contents [PDF] Effective Processor Verification with Logic Fuzzer Enhanced Co-simulation
[10] Checkpoint productivity [PDF] Effective Processor Verification with Logic Fuzzer Enhanced Co-simulation
[11] Dromajo integration [PDF] Effective Processor Verification with Logic Fuzzer Enhanced Co-simulation
[12] Deterministic checkpoint state [PDF] Effective Processor Verification with Logic Fuzzer Enhanced Co-simulation
[13] Logic Fuzzer definition [PDF] Effective Processor Verification with Logic Fuzzer Enhanced Co-simulation
[14] Logic Fuzzer table-mutator example [PDF] Effective Processor Verification with Logic Fuzzer Enhanced Co-simulation
[15] Evaluation methodology [PDF] Effective Processor Verification with Logic Fuzzer Enhanced Co-simulation
[16] Formal verification comparison [PDF] Effective Processor Verification with Logic Fuzzer Enhanced Co-simulation