Shreesha Srinath
PersonShreesha Srinath is an Intel-affiliated co-author of the 2021 MICRO-54 paper "Effective Processor Verification with Logic Fuzzer Enhanced Co-simulation," which presents tools for RISC-V processor verification including Logic Fuzzer and Dromajo.
First seen 5/27/2026
Last seen 5/28/2026
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Overview
Shreesha Srinath is listed as an Intel-affiliated author on the 2021 paper "Effective Processor Verification with Logic Fuzzer Enhanced Co-simulation". The paper appeared in the proceedings of The 54th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-54), held October 18–22, 2021, in Athens, Greece.
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2 connectionsShreesha Srinath is listed as an author of the paper.
Shreesha Srinath is affiliated with Intel.
CITATIONS
4 sources4 citations — click to collapse
[1] Shreesha Srinath is listed as an Intel-affiliated author of "Effective Processor Verification with Logic Fuzzer Enhanced Co-simulation." [PDF] Effective Processor Verification with Logic Fuzzer Enhanced Co ...
[2] The paper was published in the MICRO-54 proceedings in 2021. [PDF] Effective Processor Verification with Logic Fuzzer Enhanced Co ...
[3] The paper presents Logic Fuzzer for expanding verification-space exploration without creating additional verification tests. [PDF] Effective Processor Verification with Logic Fuzzer Enhanced Co ...
[4] The paper presents Dromajo as a RISC-V processor verification framework and RV64GC emulator designed for co-simulation. [PDF] Effective Processor Verification with Logic Fuzzer Enhanced Co ...