Overview

Shreesha Srinath is listed as an Intel-affiliated author on the 2021 paper "Effective Processor Verification with Logic Fuzzer Enhanced Co-simulation". The paper appeared in the proceedings of The 54th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-54), held October 18–22, 2021, in Athens, Greece.

Research context

The paper addresses processor verification for RISC-V cores. It presents Logic Fuzzer (LF), a tool intended to expand verification-space exploration without requiring additional verification tests, and Dromajo, described in the paper as a RISC-V processor verification framework and RV64GC emulator designed for co-simulation purposes.

Affiliation

In the paper author block, Srinath is associated with Intel, with a listed location of Portland, Oregon, USA.