Intel
OrganizationIntel appears in the provided evidence as the organizational affiliation of researchers contributing to RISC-V CPU verification research, including Fei Su and Shreesha Srinath.
First seen 5/27/2026
Last seen 7/4/2026
Evidence 6 chunks
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WIKI
Intel
Intel appears in the provided evidence as the organizational affiliation of researchers contributing to RISC-V CPU verification research.
Affiliated researchers
NEIGHBORHOOD
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explore full graph →RELATIONSHIPS
4 connectionsShreesha Srinath is affiliated with Intel.
Intel produces black-box or proprietary CPUs with microcode-level behavior that is inaccessible.
Javier S. Turek is affiliated with Intel.
Fei Su is affiliated with Intel, USA.
LINKED ENTITIES
1 linksCITATIONS
3 sources3 citations — click to collapse
[1] Fei Su is affiliated with Intel, USA, as credited in the editor's notes of the article "Randomized Testing of RISC-V CPUs Using Direct Instruction Injection." Randomized Testing of RISC-V CPUs Using Direct Instruction Injection
[2] The article presents a randomized testing framework for RISC-V implementations using direct instruction injection for test injection. Randomized Testing of RISC-V CPUs Using Direct Instruction Injection
[3] Shreesha Srinath is listed with an Intel affiliation in the 2021 MICRO-54 paper "Effective Processor Verification with Logic Fuzzer Enhanced Co-simulation," alongside co-authors Nursultan Kabylkas, Tommy Thorn, Polychronis Xekalakis, and Jose Renau, with the location given as Portland, Oregon, USA. Effective Processor Verification with Logic Fuzzer Enhanced Co-simulation