Intel

Intel appears in the provided evidence as the organizational affiliation of researchers contributing to RISC-V CPU verification research.

Affiliated researchers

Fei Su

The publication "Randomized Testing of RISC-V CPUs Using Direct Instruction Injection" (also rendered as "Randomized Testing of RISC-V CPUs using Direct Instruction Injection") credits Fei Su, Intel, USA as the author affiliation in the editor's notes. The work presents a randomized testing framework for RISC-V implementations by using a technique called direct instruction injection for test injection. The article is hosted at the Cambridge repository (https://www.repository.cam.ac.uk/items/39da5f1b-a435-4e3c-a205-39e35f80a640).

Shreesha Srinath

The previous version of this article noted that Shreesha Srinath is listed with an Intel affiliation in the 2021 MICRO-54 paper "Effective Processor Verification with Logic Fuzzer Enhanced Co-simulation," authored by Nursultan Kabylkas, Tommy Thorn, Shreesha Srinath, Polychronis Xekalakis, and Jose Renau, with the location given as Portland, Oregon, USA. That paper focuses on RISC-V processor verification and presents tools including Logic Fuzzer, which randomizes design-under-test states or control signals where functionality is not affected, and Dromajo, described as an RV64GC emulator designed for co-simulation purposes.

Research context

Across both cited works, Intel researchers are associated with RISC-V CPU verification and randomized testing methodologies, including direct instruction injection and logic-fuzzer-enhanced co-simulation.