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reference model comparison

Concept

Reference model comparison is a processor verification technique that runs code on both an implementation and a high-level golden model, then checks whether their architectural states or execution traces agree. It can be implemented as end-of-simulation comparison, trace comparison, or co-simulation, with co-simulation addressing asynchronous stimuli such as interrupts by coordinating the implementation and reference model during execution.

First seen 5/28/2026
Last seen 6/8/2026
Evidence 8 chunks
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Overview

Reference model comparison is a verification technique for processors in which the execution of an implementation is compared against a reference, or golden, model. In the cited MICRO-54 paper, the reference model is described as a high-level software model of a processor that is fast, uncomplicated, omits implementation details, and updates architectural state at instruction-level granularity. The core idea is that when the same code runs on the device under test (DUT) and the model, their architectural states should match at any given moment. [C1]

This technique is useful in settings where self-checking is difficult. For randomly generated verification code, the paper notes that self-checking techniques are not applicable because of the random nature of the tests; instead, pass/fail behavior can be determined by comparing execution with a reference model. [C2]

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RELATIONSHIPS

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The paper uses reference model comparison as a verification technique.
TestRIG ← implements 90% 1e
TestRIG compares execution traces against reference models to detect divergences.
Hardware-Software Co-Verification ← implements 85% 1e
Hardware-software co-verification compares execution against reference models.

CITATIONS

8 sources
8 citations — click to expand
[1] A reference or golden model is a high-level software processor model that is fast, uncomplicated, omits implementation details, and changes architectural state at instruction-level granularity; reference model comparison checks that the implementation and model follow matching execution paths and architectural states. [PDF] Effective Processor Verification with Logic Fuzzer Enhanced Co ...
[2] For randomly generated verification tests, self-checking techniques are not applicable due to the random nature of the generated tests, so execution can be compared with a reference model. [PDF] Effective Processor Verification with Logic Fuzzer Enhanced Co ...
[3] End-of-simulation comparison runs the same code on the reference model and RTL implementation, dumps register-file and memory state at the end, and compares them; its drawbacks include hidden overwritten bugs and difficult debugging far from the divergence point. [PDF] Effective Processor Verification with Logic Fuzzer Enhanced Co ...
[4] Trace comparison requires both models to dump execution logs, typically including program-counter flow and register or memory writebacks, and flags mismatches between the traces. [PDF] Effective Processor Verification with Logic Fuzzer Enhanced Co ...
[5] Trace comparison fails for asynchronous external stimuli such as interrupts and debug requests because standalone models compared after execution can produce different logs from a single interrupt. [PDF] Effective Processor Verification with Logic Fuzzer Enhanced Co ...
[6] Co-simulation runs the models in parallel with communication; at events such as instruction commit, the RTL signals the reference to commit and compare state, and a failed comparison immediately halts execution and reports the stimulus. [PDF] Effective Processor Verification with Logic Fuzzer Enhanced Co ...
[7] To support asynchronous interrupts in co-simulation, the setup must allow messaging that overwrites the emulator execution path; when the RTL flags an interrupt, it informs the emulator to follow that path. [PDF] Effective Processor Verification with Logic Fuzzer Enhanced Co ...
[8] Formal verification exhaustively examines execution paths but has scalability limits for complex processors, while simulation-based verification is scalable but covers only a finite set of execution paths driven by supplied stimuli. [PDF] Effective Processor Verification with Logic Fuzzer Enhanced Co ...