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end-of-simulation comparison

Concept

End-of-simulation comparison is a reference-model checking method for processor verification in which the same code is run on both the RTL design under test and a golden reference model, and their architectural states are compared only after the test completes. It is simple and inexpensive, but can hide bugs whose architectural effects are later overwritten and can make debugging difficult because the detected mismatch may be far from the original divergence.

First seen 5/27/2026
Last seen 5/28/2026
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Definition

End-of-simulation comparison is a reference-model comparison technique used in processor verification. It runs the same code on both a reference, or golden, processor model and the RTL implementation, then compares their architectural state only after the simulation finishes.[1]

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Effective Processor Verification with Logic Fuzzer Enhanced Co-simulation ← uses 85% 1e
The paper discusses end-of-simulation comparison as a simpler verification approach.

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Effective Processor Verification with Logic Fuzzer Enhanced Co-simulation USES Extracted graph relationship

CITATIONS

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[1] End-of-simulation comparison runs the same code on the reference model and RTL implementation, then compares final architectural state by dumping register-file state and memory at the end of simulation. [PDF] Effective Processor Verification with Logic Fuzzer Enhanced Co ...
[2] The cited paper characterizes end-of-simulation comparison as cheap and simplistic, and identifies drawbacks: overwritten buggy architectural effects can be hidden, and detected mismatches can be difficult to debug because they may be far from the point of divergence. [PDF] Effective Processor Verification with Logic Fuzzer Enhanced Co ...
[3] Trace comparison uses execution logs such as program-counter flow and register or memory writebacks, while co-simulation runs both models in parallel and can halt on a failed comparison near the divergence. [PDF] Effective Processor Verification with Logic Fuzzer Enhanced Co ...