BOOM
CodeArtifactBOOM is a UC Berkeley Berkeley Architecture Research Group RISC-V core generator written in Chisel. In the MICRO-54 paper “Effective Processor Verification with Logic Fuzzer Enhanced Co-simulation,” the authors evaluated Dromajo and Logic Fuzzer–enhanced co-simulation on BOOM alongside CVA6 and BlackParrot, using the default MediumBoomConfig as a 2-wide out-of-order RV64GC core. The study describes Dromajo integration through BOOM’s reorder buffer, Logic Fuzzer congestor insertion enabled by BOOM’s Chisel/FIRRTL flow, and a BOOM mtval exception-reporting bug that was later absent in newer commits.
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BOOM
BOOM is a RISC-V core generator developed and maintained at UC Berkeley’s Berkeley Architecture Research group. In the cited evaluation, BOOM is described as written in the Chisel hardware construction language and configurable to generate Verilog BOOM designs with varying complexity. The generated cores implement the 64-bit RISC-V instruction set. The evaluation used the default MediumBoomConfig, characterized in the paper as a 2-wide, out-of-order RV64GC core supporting M, S, and U privilege modes with SV39 virtual memory; the paper also notes that a more complex BOOM configuration had been taped out in 28 nm technology. [c1]
Role in Dromajo and Logic Fuzzer evaluation
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