HARTBREAKER
ToolFirst seen 7/3/2026
Last seen 7/3/2026
Evidence 18 chunks
NEIGHBORHOOD
No graph connections found for this entity yet. It may appear in future ingestion runs.
explore full graph →RELATIONSHIPS
21 connectionsHARTBREAKER uses RTL simulation to test CPU designs.
HARTBREAKER was evaluated on the XiangShan RISC-V CPU.
HARTBREAKER uses litmus tests to verify memory consistency model compliance.
HARTBREAKER uses an instruction set simulator (Spike) as a golden model.
HARTBREAKER was evaluated on the NaxRiscv CPU.
HARTBREAKER was evaluated on the Rocket RISC-V CPU.
HARTBREAKER was evaluated on the BOOM RISC-V CPU.
HARTBREAKER was evaluated on the Toooba RISC-V CPU.
HARTBREAKER is designed for high instruction throughput.
The HARTBREAKER paper introduces the HARTBREAKER multi-hart RISC-V CPU fuzzer.
HARTBREAKER implements determinism anchors to manage non-determinism.
HARTBREAKER implements control-flow anchors to handle control-flow non-determinism.
HARTBREAKER implements data-flow anchors to handle data-flow non-determinism.
HARTBREAKER implements synchronization anchors to bound non-determinism for verification.
HARTBREAKER is a pre-silicon fuzzer for multi-hart RISC-V CPUs.
HARTBREAKER uses Spike as a golden model ISS.
HARTBREAKER is compared to Cascade in terms of instruction diversity.
HARTBREAKER, like other fuzzers, relies on differential testing using an ISS or reference hart.
HARTBREAKER is compared against RISCV-DV in terms of coverage and capabilities.
HARTBREAKER discovered a bug related to mret instruction handling in Toooba.
HARTBREAKER uses Verilator to simulate designs under test.