Rocket — STIMSMITH

Rocket

CodeArtifact

Rocket is a real-world open-source RISC-V processor used as an evaluation target for MorFuzz. In the MorFuzz study, Rocket is notable for supporting delayed write-back, which affects co-simulation-based state comparison because long-latency instruction results may not be ready at commit.

First seen 5/27/2026

Last seen 6/6/2026

Evidence 10 chunks

Wiki v1

WIKI

Overview

Rocket is identified in the MorFuzz USENIX Security 2023 paper as one of three real-world open-source processors used to evaluate a RISC-V prototype of MorFuzz, alongside CVA6 and BOOM. The evaluated processors are described collectively as covering microarchitectures ranging from simple in-order cores to complex out-of-order superscalar cores. [citation: rocket-morfuzz-evaluation]

Role in MorFuzz evaluation

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NEIGHBORHOOD

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RELATIONSHIPS

4 connections

MorFuzz ← evaluates 100% 4e

MorFuzz is evaluated on the Rocket RISC-V processor and discovers bugs in it.

UC Berkeley authored by → 100% 1e

Rocket is the world's first RISC-V processor open sourced by UC Berkeley.

RISC-V ISA implements → 100% 1e

Rocket is a RISC-V processor implementing the RISC-V ISA.

UC Berkeley published by → 100% 1e

Rocket was open sourced by UC Berkeley.

LINKED ENTITIES

2 links

MorFuzz EVALUATES Extracted graph relationship

UC Berkeley AUTHORED_BY Extracted graph relationship

CITATIONS

3 sources

3 citations — click to collapse

[1] rocket-morfuzz-evaluation MorFuzz: Fuzzing Processor via Runtime Instruction Morphing enhanced Synchronizable Co-simulation

[2] morfuzz-evaluation-results MorFuzz: Fuzzing Processor via Runtime Instruction Morphing enhanced Synchronizable Co-simulation

[3] rocket-delayed-writeback MorFuzz: Fuzzing Processor via Runtime Instruction Morphing enhanced Synchronizable Co-simulation