Prelude

Tool

First seen 8/16/2026

Last seen 8/16/2026

Evidence 16 chunks

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RELATIONSHIPS

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BOOM evaluates → 100% 3e

Prelude is evaluated on the BOOM out-of-order superscalar RISC-V processor.

Priming-Guided State Reconstruction implements → 100% 2e

Prelude implements the priming-guided state reconstruction technique.

Snapshot-Based Debugging implements → 100% 2e

Prelude implements snapshot-based debugging by recording only essential architectural states.

differential testing implements → 100% 2e

Prelude uses differential testing to detect errors by comparing DUT against ISA simulator.

Visibility Warm-Up implements → 100% 2e

Prelude implements visibility warm-up to reconstruct micro-architectural state.

Memory Footprint Analysis implements → 100% 2e

Prelude implements memory footprint analysis to reconstruct the initial memory state.

Cycle-Accurate Replay implements → 100% 2e

Prelude enables cycle-accurate replay after warm-up.

Micro-Architectural State Reconstruction implements → 100% 2e

Prelude reconstructs micro-architectural state from lightweight snapshots via warm-up.

Data Extract Unit (DEU) uses → 100% 2e

Prelude uses the DEU as the bridge between snapshot processing and hardware replay.

Architectural Register Management Unit (AMU) uses → 100% 2e

Prelude uses the AMU to reconstruct architectural register state for replay.

Memory Rebuild Unit (MRU) uses → 100% 2e

Prelude uses the MRU to reconstruct memory state for replay.

Rocket evaluates → 100% 2e

Prelude is also evaluated on the Rocket processor core.

spike uses → 100% 2e

Prelude uses Spike as the ISA simulator reference model for differential testing.

Reproduction Rate ← part of 85% 2e

Reproduction rate is a key metric defined within the Prelude evaluation framework.

Embench uses → 100% 2e

Prelude is evaluated using Embench benchmarks.

DESSERT ← compares with 100% 2e

Prelude is compared against DESSERT as a baseline debugging approach.

ENCORE ← compares with 100% 2e

Prelude is compared against ENCORE as a baseline debugging approach.

Verilator compares with → 100% 2e

Prelude is compared against Verilator as a software simulation baseline.

Memory Footprint uses → 100% 2e

Prelude records and analyzes the memory footprint to reconstruct memory state.

Architectural Registers uses → 100% 2e

Prelude captures architectural registers as the core of its lightweight snapshot.

CoreMark uses → 100% 2e

Prelude is evaluated using CoreMark benchmarks.

Verilator uses → 100% 1e

Prelude uses Verilator for software-level replay and verification.

AMD Virtex UltraScale+ VU19P FPGA uses → 100% 1e

Prelude is implemented on an AMD Virtex UltraScale+ VU19P FPGA.

Xilinx Vivado uses → 100% 1e

Prelude uses Xilinx Vivado 2024.2 for FPGA implementation.

Prelude: Priming-Guided State Reconstruction for Efficient FPGA Processor Debugging ← introduces 100% 1e

The paper introduces the Prelude debugging framework.

PCIe Interface uses → 90% 1e

Prelude transmits snapshot data from FPGA to host via PCIe interface.

DPI-C interface uses → 95% 1e

Prelude uses the DPI-C interface for transferring data between DEU and simulation environment.