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Prelude: Priming-Guided State Reconstruction for Efficient FPGA Processor Debugging

Paper
First seen 8/16/2026
Last seen 8/16/2026
Evidence 5 chunks

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RELATIONSHIPS

16 connections
Prelude introduces → 100% 1e
The paper introduces the Prelude debugging framework.
Jialin Sun authored by → 100% 1e
Jialin Sun is listed as an author of the paper.
Yuchen Hu authored by → 100% 1e
Yuchen Hu is listed as an author of the paper.
Dean You authored by → 100% 1e
Dean You is listed as an author of the paper.
Zhe Jiang authored by → 100% 1e
Zhe Jiang is the corresponding author of the paper.
Xinwei Fang authored by → 100% 1e
Xinwei Fang is listed as an author of the paper.
Southeast University authored by → 100% 1e
The paper is affiliated with Southeast University.
University of York authored by → 100% 1e
The paper is affiliated with University of York.
National Center of Technology Innovation for EDA authored by → 100% 1e
The paper is affiliated with the National Center of Technology Innovation for EDA.
riscv-dv mentions → 90% 1e
The paper cites RISC-V DV as a related work.
ProcessorFuzz mentions → 90% 1e
The paper cites ProcessorFuzz as related work.
HyPFuzz mentions → 90% 1e
The paper cites HyPFuzz as related work.
ISAAC mentions → 85% 1e
The paper cites ISAAC as related work on CPU verification with FPGA.
MEIC mentions → 85% 1e
The paper cites MEIC as related work on RTL debug automation.
DiffTest-H mentions → 85% 1e
The paper cites DiffTest-H as related work on processor verification.
RISCVuzz mentions → 85% 1e
The paper cites RISCVuzz as related work on CPU vulnerability discovery.