DiffTest-H

Tool

First seen 8/7/2026

Last seen 8/16/2026

Evidence 9 chunks

NEIGHBORHOOD

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RELATIONSHIPS

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agile verification mentions → 93% 2e

DiffTest-H aims to advance agile verification for processors.

Xiangshan Team ← introduces 97% 2e

The Xiangshan team developed and introduced DiffTest-H.

Software-Hardware Communication Overhead depends on → 92% 2e

DiffTest-H's design is motivated by and addresses the challenge of software-hardware communication overhead.

Squash Compression implements → 99% 2e

DiffTest-H includes Squash as one of its three design points for reducing transmission data volume.

Replay Debugging implements → 99% 2e

DiffTest-H includes Replay as one of its three design points for maintaining instruction-level error debugging granularity.

DiffTest extends → 99% 2e

DiffTest-H extends DiffTest with semantic-aware hardware-accelerated co-simulation.

Semantic-Aware Communication implements → 99% 2e

DiffTest-H implements semantic-aware communication to optimize software-hardware communication overhead.

Palladium uses → 97% 2e

DiffTest-H runs RTL on Palladium for hardware-accelerated simulation.

FPGA uses → 97% 2e

DiffTest-H runs RTL on FPGA for hardware-accelerated simulation.

Xiangshan Processor evaluates → 99% 2e

DiffTest-H is applied in the verification of the Xiangshan processor, discovering over 150 bugs.

Hardware-Accelerated RTL Simulation implements → 97% 2e

DiffTest-H uses hardware simulation platforms to accelerate RTL simulation.

Fromajo compares with → 96% 2e

DiffTest-H is compared against Fromajo as the existing SOTA co-simulation tool.

DiffTest-H: Toward Semantic-Aware Communication in Hardware-Accelerated Co-Simulation ← introduces 99% 2e

The paper introduces DiffTest-H as a new semantic-aware hardware-accelerated co-simulation framework.

Batch Packaging implements → 99% 2e

DiffTest-H includes Batch as one of its three design points for optimizing communication frequency.

Prelude: Priming-Guided State Reconstruction for Efficient FPGA Processor Debugging ← mentions 85% 1e

The paper cites DiffTest-H as related work on processor verification.

NEMU uses → 97% 1e

DiffTest-H runs NEMU as the reference model on x86 while RTL runs on hardware.

Xiangshan Processor ← uses 98% 1e

DiffTest-H is applied in the actual development process of the Xiangshan processor.

PCIe uses → 88% 1e

DiffTest-H uses PCIe as the software-hardware pathway in FPGA-based configurations.

Co-Simulation implements → 99% 1e

DiffTest-H is a hardware-accelerated co-simulation framework.

differential testing implements → 95% 1e

DiffTest-H is a hardware-accelerated processor verification tool using differential testing.