DiffTest

Tool

First seen 6/6/2026

Last seen 8/7/2026

Evidence 12 chunks

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18 connections

Co-simulation uses → 100% 2e

DiffTest is a co-simulation framework for processor verification.

DiffTest covers 32 types of verification events.

DiffTest-H ← extends 99% 2e

DiffTest-H extends DiffTest with semantic-aware hardware-accelerated co-simulation.

DPI-C interface uses → 90% 2e

DiffTest uses individual DPI-C functions for each verification event.

DiffTest-H ← compares with 100% 2e

DiffTest-H is compared to the baseline DiffTest framework for speedup.

Difftest compares architectural states between DUT and REF to detect bugs.

NEMU uses → 98% 1e

Difftest uses NEMU as the reference model for co-simulation.

RTL uses → 95% 1e

Difftest operates on an RTL processor, monitoring instruction commits and state updates.

coremark workload evaluates → 93% 1e

Difftest is used to run and verify the coremark workload on XiangShan.

waveform dump implements → 92% 1e

Difftest supports dumping waveforms when a bug is detected.

XiangShan evaluates → 97% 1e

Difftest is used to verify the XiangShan processor implementation.

XiangShan ← uses 97% 1e

XiangShan uses Difftest for ISA co-simulation based verification.

The Xiangshan MICRO 2022 paper mentioned DiffTest as an important component.

Xiangshan Team ← introduces 90% 1e

The Xiangshan team used and promoted DiffTest as part of their verification methodology.

differential testing implements → 98% 1e

DiffTest implements the differential testing technique for chip functional verification.

Co-Simulation implements → 97% 1e

DiffTest is a co-simulation verification framework.

Yu Zihao authored by → 99% 1e

DiffTest was originally designed by Dr. Yu Zihao in 2017.

ISA co-simulation implements → 99% 1e

Difftest is explicitly described as an ISA co-simulation framework.