Overview

Architectural state comparison is a core verification methodology employed in the XiangShan processor development flow. It involves continuously comparing the visible architectural state (registers, program counter, memory, and other ISA-level state) of a hardware design under test (DUT) against a trusted reference model (REF) as instructions are committed and state updates occur.

When any difference is detected between the two states, the simulation halts and reports the discrepancy; otherwise, simulation continues uninterrupted. This approach enables fast, automated detection of RTL bugs in out-of-order, superscalar processor designs.